Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	219596	1		T1	4		T3	11		T7	17
full_word	530851	1		T1	7		T3	5		T7	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	750137	1		T1	11		T3	16		T7	21
auto[TlIntgErrCmd]	92	1		T40	5		T78	4		T104	8
auto[TlIntgErrData]	123	1		T40	8		T78	6		T104	7
auto[TlIntgErrBoth]	95	1		T40	7		T104	5		T81	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	447741	1		T1	10		T5	8		T27	8
auto[1]	302706	1		T1	1		T3	16		T7	21

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	177206	1		T1	3		T5	4		T27	3
auto[TlIntgErrNone]	partial	auto[1]	42100	1		T1	1		T3	11		T7	17
auto[TlIntgErrNone]	full_word	auto[0]	270390	1		T1	7		T5	4		T27	5
auto[TlIntgErrNone]	full_word	auto[1]	260441	1		T3	5		T7	4		T8	3
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T40	2		T78	2		T104	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T40	3		T78	1		T104	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T78	1		T88	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T104	1		T76	1		T137	1
auto[TlIntgErrData]	partial	auto[0]	56	1		T40	2		T78	3		T104	4
auto[TlIntgErrData]	partial	auto[1]	60	1		T40	6		T78	2		T104	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T135	1		T77	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T78	1		T135	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T104	1		T81	1		T94	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T40	6		T104	4		T81	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T88	1		T138	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T40	1		T88	1		T139	1