Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T14
11CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT20,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8263501 8262699 0 0
selKnown1 9700495 9699693 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8263501 8262699 0 0
T1 1626 1624 0 0
T2 310 308 0 0
T3 14044 14042 0 0
T4 818 816 0 0
T5 16 14 0 0
T6 0 15 0 0
T7 39808 39806 0 0
T9 0 8 0 0
T15 2 0 0 0
T17 7496 7494 0 0
T18 0 3 0 0
T19 2 0 0 0
T20 0 9 0 0
T30 42 40 0 0
T31 0 42 0 0
T32 0 40 0 0
T33 324 322 0 0
T34 362 360 0 0
T35 358 356 0 0
T38 2 0 0 0
T45 356 354 0 0
T57 2 0 0 0
T62 0 10 0 0
T66 0 20 0 0
T67 2 0 0 0
T68 2 0 0 0
T69 2 0 0 0
T70 2 0 0 0
T131 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 9700495 9699693 0 0
T1 2773 2771 0 0
T2 1398 1396 0 0
T3 56523 56521 0 0
T4 1861 1859 0 0
T5 16 14 0 0
T6 0 4 0 0
T7 99326 99324 0 0
T9 0 6 0 0
T14 0 10 0 0
T15 2 0 0 0
T17 20052 20050 0 0
T19 2 0 0 0
T20 0 10 0 0
T30 42 40 0 0
T31 0 40 0 0
T32 0 40 0 0
T33 1993 1991 0 0
T34 1546 1544 0 0
T35 2660 2658 0 0
T38 2 0 0 0
T45 1851 1849 0 0
T57 2 0 0 0
T62 0 20 0 0
T66 0 20 0 0
T67 2 0 0 0
T68 2 0 0 0
T69 2 0 0 0
T70 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T14
11CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 511090 510993 0 0
selKnown1 1948189 1948092 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 511090 510993 0 0
T1 813 812 0 0
T2 155 154 0 0
T3 7022 7021 0 0
T4 409 408 0 0
T7 19904 19903 0 0
T17 3748 3747 0 0
T33 162 161 0 0
T34 181 180 0 0
T35 179 178 0 0
T45 178 177 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1948092 0 0
T1 1960 1959 0 0
T2 1243 1242 0 0
T3 49501 49500 0 0
T4 1452 1451 0 0
T7 79422 79421 0 0
T17 16304 16303 0 0
T33 1831 1830 0 0
T34 1365 1364 0 0
T35 2481 2480 0 0
T45 1673 1672 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T14
11CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 217 120 0 0
selKnown1 207 110 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 217 120 0 0
T5 8 7 0 0
T6 0 4 0 0
T9 0 3 0 0
T14 0 5 0 0
T15 1 0 0 0
T19 1 0 0 0
T20 0 4 0 0
T30 21 20 0 0
T31 0 22 0 0
T32 0 20 0 0
T38 1 0 0 0
T57 1 0 0 0
T62 0 10 0 0
T66 0 10 0 0
T67 1 0 0 0
T68 1 0 0 0
T69 1 0 0 0
T70 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 207 110 0 0
T5 8 7 0 0
T6 0 2 0 0
T9 0 3 0 0
T14 0 5 0 0
T15 1 0 0 0
T19 1 0 0 0
T20 0 5 0 0
T30 21 20 0 0
T31 0 20 0 0
T32 0 20 0 0
T38 1 0 0 0
T57 1 0 0 0
T62 0 10 0 0
T66 0 10 0 0
T67 1 0 0 0
T68 1 0 0 0
T69 1 0 0 0
T70 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T14
11CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT20,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7750715 7750411 0 0
selKnown1 7750715 7750411 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7750715 7750411 0 0
T1 813 812 0 0
T2 155 154 0 0
T3 7022 7021 0 0
T4 409 408 0 0
T7 19904 19903 0 0
T17 3748 3747 0 0
T33 162 161 0 0
T34 181 180 0 0
T35 179 178 0 0
T45 178 177 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 7750715 7750411 0 0
T1 813 812 0 0
T2 155 154 0 0
T3 7022 7021 0 0
T4 409 408 0 0
T7 19904 19903 0 0
T17 3748 3747 0 0
T33 162 161 0 0
T34 181 180 0 0
T35 179 178 0 0
T45 178 177 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T14
11CoveredT20,T14

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT20,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1479 1175 0 0
selKnown1 1384 1080 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1479 1175 0 0
T5 8 7 0 0
T6 0 11 0 0
T9 0 5 0 0
T15 1 0 0 0
T18 0 3 0 0
T19 1 0 0 0
T20 0 5 0 0
T30 21 20 0 0
T31 0 20 0 0
T32 0 20 0 0
T38 1 0 0 0
T57 1 0 0 0
T66 0 10 0 0
T67 1 0 0 0
T68 1 0 0 0
T69 1 0 0 0
T70 1 0 0 0
T131 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1384 1080 0 0
T5 8 7 0 0
T6 0 2 0 0
T9 0 3 0 0
T14 0 5 0 0
T15 1 0 0 0
T19 1 0 0 0
T20 0 5 0 0
T30 21 20 0 0
T31 0 20 0 0
T32 0 20 0 0
T38 1 0 0 0
T57 1 0 0 0
T62 0 10 0 0
T66 0 10 0 0
T67 1 0 0 0
T68 1 0 0 0
T69 1 0 0 0
T70 1 0 0 0

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