Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	55.00			55.00
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.00			55.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.00			55.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T2,*T17	Yes	T1,T2,T3	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T33	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T3	OUTPUT
syndrome_o[6:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T7	OUTPUT
err_o[1:0]	Yes	Yes	T1,T2,T35	Yes	T1,T2,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	143	55.00
Total Bits 0->1	130	72	55.38
Total Bits 1->0	130	71	54.62

Ports	4	2	50.00
Port Bits	260	143	55.00
Port Bits 0->1	130	72	55.38
Port Bits 1->0	130	71	54.62

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T7,*T8,*T57	Yes	T9,T62,T14	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T9,T62,T14	Yes	T7,T8,T46	INPUT
data_o[11:0]	Yes	Yes	*T7,*T8,*T57	Yes	T9,T62,T14	OUTPUT
data_o[12]	No	No		Yes	T46	OUTPUT
data_o[18:13]	Yes	Yes	*T76,*T77,*T78	Yes	T79,T76,T77	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[24:20]	Yes	Yes	*T14,*T80,*T81	Yes	T14,T80,T82	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[43:26]	Yes	Yes	*T83,*T77,*T84	Yes	T83,T77,T85	OUTPUT
data_o[44]	No	No		No		OUTPUT
data_o[52:45]	Yes	Yes	*T86,*T81,*T84	Yes	T86,T81,T84	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[54]	Yes	Yes	*T76	Yes	T87,T76	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[56]	Yes	Yes	T78,T88	Yes	T78,T88	OUTPUT
syndrome_o[6:0]	Yes	Yes	T9,T62,T14	Yes	T46,T15,T9	OUTPUT
err_o[1:0]	Yes	Yes	T9,T62,T14	Yes	T7,T8,T46	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T17,*T35	Yes	T2,T35,T38	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T33,T35	Yes	T2,T17,T33	INPUT
data_o[56:0]	Yes	Yes	T2,T17,T35	Yes	T2,T35,T38	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T17,T35	Yes	T2,T35,T8	OUTPUT
err_o[1:0]	Yes	Yes	T2,T35,T38	Yes	T2,T35,T8	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T7,*T8	Yes	T1,T3,T7	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
data_o[56:0]	Yes	Yes	T1,T7,T8	Yes	T1,T3,T7	OUTPUT
syndrome_o[6:0]	Yes	Yes	T1,T7,T8	Yes	T1,T7,T47	OUTPUT
err_o[1:0]	Yes	Yes	T1,T3,T7	Yes	T1,T7,T8	OUTPUT

*Tests covering at least one bit in the range