Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 213044 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 603129 1 T6 10 T7 7 T20 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 506344 1 T8 10 T17 80 T27 8
values[0x0] 152619 1 T6 21 T7 16 T20 1
values[0x1] 157210 1 T6 24 T7 12 T20 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 163062 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 653111 1 T6 14 T7 9 T20 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3487 1 T17 1 T18 2 T49 6
valid_sources[0x01] 2898 1 T6 4 T18 2 T29 1
valid_sources[0x02] 2934 1 T6 2 T49 7 T50 24
valid_sources[0x03] 3440 1 T17 1 T49 11 T50 30
valid_sources[0x04] 2945 1 T49 13 T50 16 T53 182
valid_sources[0x05] 2867 1 T17 3 T49 23 T53 223
valid_sources[0x06] 3457 1 T49 6 T50 52 T53 216
valid_sources[0x07] 3221 1 T6 1 T8 1 T21 1
valid_sources[0x08] 2906 1 T7 2 T8 1 T29 1
valid_sources[0x09] 2746 1 T22 1 T18 3 T49 16
valid_sources[0x0a] 3207 1 T6 2 T49 9 T50 6
valid_sources[0x0b] 2607 1 T17 1 T18 1 T49 13
valid_sources[0x0c] 4362 1 T18 1 T49 9 T53 184
valid_sources[0x0d] 3565 1 T21 1 T13 2 T49 11
valid_sources[0x0e] 3520 1 T49 12 T50 11 T53 193
valid_sources[0x0f] 3064 1 T22 1 T43 2 T49 8
valid_sources[0x10] 3345 1 T49 15 T53 204 T45 16
valid_sources[0x11] 3607 1 T8 1 T18 2 T49 3
valid_sources[0x12] 2849 1 T6 1 T49 10 T50 8
valid_sources[0x13] 3295 1 T17 1 T49 7 T53 233
valid_sources[0x14] 2486 1 T31 2 T49 8 T50 4
valid_sources[0x15] 3152 1 T18 1 T49 10 T50 32
valid_sources[0x16] 3382 1 T28 7 T49 20 T50 10
valid_sources[0x17] 3377 1 T7 4 T17 1 T13 1
valid_sources[0x18] 2895 1 T17 1 T12 8 T49 8
valid_sources[0x19] 3309 1 T31 1 T49 18 T50 62
valid_sources[0x1a] 3231 1 T17 3 T18 1 T49 12
valid_sources[0x1b] 3235 1 T17 1 T49 16 T50 7
valid_sources[0x1c] 3329 1 T49 9 T53 207 T45 31
valid_sources[0x1d] 3340 1 T49 10 T50 36 T53 225
valid_sources[0x1e] 3253 1 T18 2 T49 7 T50 2
valid_sources[0x1f] 3766 1 T17 1 T31 2 T49 10
valid_sources[0x20] 3649 1 T49 18 T53 221 T45 18
valid_sources[0x21] 3192 1 T18 1 T31 1 T49 9
valid_sources[0x22] 3144 1 T8 1 T21 1 T49 9
valid_sources[0x23] 3924 1 T18 2 T31 1 T49 10
valid_sources[0x24] 3827 1 T49 7 T53 177 T45 34
valid_sources[0x25] 2998 1 T49 6 T53 211 T45 19
valid_sources[0x26] 2704 1 T49 18 T53 211 T45 22
valid_sources[0x27] 3361 1 T17 1 T49 11 T50 26
valid_sources[0x28] 3169 1 T18 1 T49 11 T50 17
valid_sources[0x29] 2967 1 T49 9 T50 56 T53 194
valid_sources[0x2a] 3103 1 T31 2 T49 10 T50 39
valid_sources[0x2b] 3421 1 T22 3 T11 1 T49 12
valid_sources[0x2c] 3478 1 T7 4 T49 14 T50 1
valid_sources[0x2d] 3812 1 T6 1 T18 1 T49 6
valid_sources[0x2e] 3530 1 T49 10 T50 15 T53 194
valid_sources[0x2f] 3142 1 T49 15 T50 96 T53 207
valid_sources[0x30] 2764 1 T49 11 T53 226 T45 14
valid_sources[0x31] 3223 1 T17 1 T49 15 T53 207
valid_sources[0x32] 3188 1 T49 20 T53 215 T45 21
valid_sources[0x33] 2883 1 T18 3 T49 13 T53 200
valid_sources[0x34] 3021 1 T31 2 T49 9 T53 197
valid_sources[0x35] 2832 1 T17 1 T18 1 T43 1
valid_sources[0x36] 2805 1 T17 2 T21 1 T18 2
valid_sources[0x37] 3366 1 T18 1 T31 3 T49 7
valid_sources[0x38] 2762 1 T18 2 T49 6 T50 57
valid_sources[0x39] 2896 1 T6 1 T49 13 T53 198
valid_sources[0x3a] 3449 1 T11 7 T49 21 T53 215
valid_sources[0x3b] 2938 1 T49 16 T50 9 T53 189
valid_sources[0x3c] 2943 1 T12 5 T31 3 T49 15
valid_sources[0x3d] 3341 1 T17 3 T49 7 T53 220
valid_sources[0x3e] 3484 1 T49 8 T50 8 T53 189
valid_sources[0x3f] 2896 1 T13 1 T49 13 T53 220
valid_sources[0x40] 3182 1 T17 1 T49 8 T50 10
valid_sources[0x41] 3200 1 T18 3 T49 9 T53 221
valid_sources[0x42] 3505 1 T8 2 T18 1 T49 15
valid_sources[0x43] 2710 1 T7 2 T49 8 T53 182
valid_sources[0x44] 3073 1 T18 1 T49 11 T50 6
valid_sources[0x45] 3711 1 T49 11 T50 5 T53 221
valid_sources[0x46] 2484 1 T21 1 T139 1 T49 15
valid_sources[0x47] 3077 1 T6 2 T49 7 T50 27
valid_sources[0x48] 3118 1 T17 1 T49 12 T53 232
valid_sources[0x49] 4596 1 T24 1 T49 15 T50 11
valid_sources[0x4a] 2982 1 T49 14 T53 230 T45 26
valid_sources[0x4b] 3479 1 T31 2 T49 9 T53 196
valid_sources[0x4c] 3097 1 T17 1 T18 2 T49 18
valid_sources[0x4d] 2925 1 T18 1 T49 13 T50 49
valid_sources[0x4e] 4852 1 T17 1 T31 2 T49 11
valid_sources[0x4f] 3328 1 T6 1 T49 18 T53 188
valid_sources[0x50] 3545 1 T49 9 T50 38 T53 216
valid_sources[0x51] 3919 1 T13 1 T49 4 T50 3
valid_sources[0x52] 3439 1 T8 1 T17 1 T14 9
valid_sources[0x53] 3675 1 T49 8 T50 21 T53 214
valid_sources[0x54] 2944 1 T18 1 T140 1 T49 16
valid_sources[0x55] 2967 1 T7 1 T17 2 T49 23
valid_sources[0x56] 2828 1 T49 13 T50 1 T53 198
valid_sources[0x57] 3383 1 T49 12 T50 7 T53 229
valid_sources[0x58] 2569 1 T49 7 T53 171 T45 12
valid_sources[0x59] 2941 1 T6 1 T17 2 T22 2
valid_sources[0x5a] 3088 1 T25 1 T18 1 T49 10
valid_sources[0x5b] 3319 1 T14 6 T49 13 T50 5
valid_sources[0x5c] 2506 1 T18 1 T43 9 T49 12
valid_sources[0x5d] 3527 1 T49 14 T53 220 T45 17
valid_sources[0x5e] 2635 1 T17 1 T49 10 T53 216
valid_sources[0x5f] 3020 1 T6 1 T14 1 T18 2
valid_sources[0x60] 2875 1 T22 5 T18 1 T49 8
valid_sources[0x61] 2778 1 T17 1 T49 16 T53 225
valid_sources[0x62] 3064 1 T49 9 T50 22 T53 222
valid_sources[0x63] 3140 1 T27 8 T141 2 T49 8
valid_sources[0x64] 3646 1 T17 1 T49 15 T53 196
valid_sources[0x65] 3678 1 T8 1 T49 16 T53 197
valid_sources[0x66] 3578 1 T18 4 T31 1 T49 7
valid_sources[0x67] 2980 1 T6 1 T18 1 T11 3
valid_sources[0x68] 2409 1 T31 3 T49 15 T50 17
valid_sources[0x69] 3145 1 T11 5 T31 1 T49 17
valid_sources[0x6a] 3282 1 T7 5 T49 8 T50 11
valid_sources[0x6b] 3079 1 T17 1 T18 1 T49 6
valid_sources[0x6c] 3036 1 T49 18 T50 1 T53 217
valid_sources[0x6d] 3443 1 T6 1 T49 7 T53 225
valid_sources[0x6e] 2933 1 T49 6 T50 31 T53 213
valid_sources[0x6f] 2907 1 T12 1 T140 1 T49 11
valid_sources[0x70] 3719 1 T17 1 T49 13 T50 22
valid_sources[0x71] 2894 1 T14 4 T21 1 T25 1
valid_sources[0x72] 3495 1 T6 1 T11 9 T49 12
valid_sources[0x73] 3906 1 T7 3 T140 2 T49 22
valid_sources[0x74] 3060 1 T18 1 T11 14 T49 13
valid_sources[0x75] 2940 1 T49 10 T50 55 T53 205
valid_sources[0x76] 3061 1 T12 1 T49 11 T50 18
valid_sources[0x77] 3158 1 T49 16 T50 14 T53 205
valid_sources[0x78] 2963 1 T8 1 T17 1 T49 7
valid_sources[0x79] 2883 1 T49 16 T50 3 T53 227
valid_sources[0x7a] 3002 1 T49 9 T50 34 T53 173
valid_sources[0x7b] 3342 1 T18 2 T49 10 T53 204
valid_sources[0x7c] 2819 1 T49 6 T53 236 T45 15
valid_sources[0x7d] 2867 1 T6 3 T49 14 T50 7
valid_sources[0x7e] 4207 1 T49 3 T50 49 T53 231
valid_sources[0x7f] 3480 1 T18 3 T11 13 T49 6
valid_sources[0x80] 3011 1 T11 1 T31 4 T49 8



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 302143 1 T8 6 T17 80 T27 4
values[0x0] all_enables biggest_size 150663 1 T6 7 T7 7 T20 1
values[0x1] all_enables biggest_size 150323 1 T6 3 T20 1 T21 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5264 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21442 1 T1 1 T41 2 T42 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 10428 1 T49 23 T50 14 T53 284
values[0x0] 7989 1 T1 1 T41 2 T42 3
values[0x1] 8289 1 T1 2 T41 4 T42 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4082 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 22624 1 T1 1 T41 2 T42 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 83 1 T53 1 T75 2 T98 8
valid_sources[0x01] 250 1 T121 1 T53 1 T48 3
valid_sources[0x02] 133 1 T142 1 T143 8 T53 2
valid_sources[0x03] 71 1 T82 5 T98 1 T76 2
valid_sources[0x04] 88 1 T47 3 T73 5 T98 3
valid_sources[0x05] 92 1 T54 17 T52 1 T144 1
valid_sources[0x06] 98 1 T91 1 T121 2 T48 1
valid_sources[0x07] 79 1 T49 10 T47 2 T73 2
valid_sources[0x08] 88 1 T53 2 T48 1 T47 1
valid_sources[0x09] 78 1 T53 1 T48 1 T73 2
valid_sources[0x0a] 88 1 T19 2 T53 1 T98 1
valid_sources[0x0b] 97 1 T53 4 T47 1 T75 5
valid_sources[0x0c] 193 1 T53 6 T73 2 T98 2
valid_sources[0x0d] 96 1 T64 6 T56 2 T145 18
valid_sources[0x0e] 75 1 T53 3 T48 1 T47 1
valid_sources[0x0f] 105 1 T53 1 T48 1 T75 1
valid_sources[0x10] 111 1 T4 1 T53 2 T48 1
valid_sources[0x11] 112 1 T53 1 T82 5 T85 1
valid_sources[0x12] 111 1 T53 1 T47 1 T75 3
valid_sources[0x13] 120 1 T146 1 T48 1 T73 1
valid_sources[0x14] 81 1 T48 1 T82 2 T73 1
valid_sources[0x15] 81 1 T146 1 T48 1 T82 2
valid_sources[0x16] 98 1 T52 2 T147 2 T146 2
valid_sources[0x17] 85 1 T53 1 T48 2 T47 1
valid_sources[0x18] 77 1 T53 2 T48 1 T47 1
valid_sources[0x19] 87 1 T53 1 T48 1 T45 10
valid_sources[0x1a] 85 1 T1 1 T53 1 T98 2
valid_sources[0x1b] 137 1 T50 3 T53 1 T48 1
valid_sources[0x1c] 96 1 T53 1 T98 4 T77 3
valid_sources[0x1d] 66 1 T4 3 T52 2 T48 1
valid_sources[0x1e] 153 1 T53 2 T48 1 T75 1
valid_sources[0x1f] 91 1 T50 1 T48 1 T83 3
valid_sources[0x20] 157 1 T51 1 T53 1 T48 1
valid_sources[0x21] 83 1 T89 7 T146 1 T47 1
valid_sources[0x22] 85 1 T144 1 T53 2 T48 1
valid_sources[0x23] 72 1 T64 1 T121 1 T73 5
valid_sources[0x24] 120 1 T53 2 T48 1 T85 3
valid_sources[0x25] 88 1 T142 1 T148 2 T53 1
valid_sources[0x26] 95 1 T53 1 T82 8 T47 2
valid_sources[0x27] 118 1 T142 1 T48 1 T73 8
valid_sources[0x28] 102 1 T74 2 T58 1 T75 1
valid_sources[0x29] 64 1 T149 1 T73 1 T75 1
valid_sources[0x2a] 101 1 T53 3 T85 2 T98 7
valid_sources[0x2b] 85 1 T50 3 T53 5 T48 1
valid_sources[0x2c] 92 1 T53 1 T48 2 T85 3
valid_sources[0x2d] 62 1 T4 1 T53 1 T76 1
valid_sources[0x2e] 74 1 T53 1 T48 1 T45 3
valid_sources[0x2f] 79 1 T48 1 T77 6 T150 1
valid_sources[0x30] 109 1 T121 1 T53 1 T73 1
valid_sources[0x31] 139 1 T53 1 T98 3 T76 4
valid_sources[0x32] 201 1 T53 3 T48 1 T46 152
valid_sources[0x33] 143 1 T53 2 T87 1 T73 5
valid_sources[0x34] 92 1 T151 2 T53 1 T48 1
valid_sources[0x35] 110 1 T48 1 T73 1 T98 1
valid_sources[0x36] 87 1 T152 1 T48 1 T47 1
valid_sources[0x37] 77 1 T142 1 T48 1 T73 10
valid_sources[0x38] 138 1 T53 1 T45 9 T47 4
valid_sources[0x39] 63 1 T53 3 T47 2 T98 1
valid_sources[0x3a] 81 1 T53 5 T48 1 T73 1
valid_sources[0x3b] 59 1 T48 1 T82 1 T98 3
valid_sources[0x3c] 152 1 T53 1 T73 5 T98 4
valid_sources[0x3d] 83 1 T50 1 T53 1 T85 1
valid_sources[0x3e] 69 1 T48 1 T98 3 T79 4
valid_sources[0x3f] 99 1 T47 2 T75 1 T98 3
valid_sources[0x40] 161 1 T144 2 T152 1 T48 2
valid_sources[0x41] 75 1 T53 4 T47 4 T73 1
valid_sources[0x42] 112 1 T52 2 T73 4 T98 2
valid_sources[0x43] 79 1 T73 3 T98 6 T76 2
valid_sources[0x44] 87 1 T1 2 T53 2 T82 1
valid_sources[0x45] 109 1 T53 1 T48 1 T75 1
valid_sources[0x46] 131 1 T53 1 T47 1 T75 1
valid_sources[0x47] 65 1 T75 1 T98 4 T76 2
valid_sources[0x48] 94 1 T53 1 T48 2 T98 4
valid_sources[0x49] 83 1 T148 1 T53 1 T47 2
valid_sources[0x4a] 94 1 T53 1 T48 1 T47 2
valid_sources[0x4b] 100 1 T48 1 T73 1 T75 2
valid_sources[0x4c] 72 1 T53 1 T47 2 T75 2
valid_sources[0x4d] 79 1 T144 1 T98 5 T115 3
valid_sources[0x4e] 83 1 T53 3 T48 1 T73 1
valid_sources[0x4f] 77 1 T47 1 T75 2 T98 5
valid_sources[0x50] 113 1 T153 10 T73 1 T75 1
valid_sources[0x51] 84 1 T53 1 T48 2 T98 2
valid_sources[0x52] 136 1 T47 1 T73 1 T98 2
valid_sources[0x53] 109 1 T154 1 T48 1 T75 2
valid_sources[0x54] 50 1 T53 2 T48 1 T75 1
valid_sources[0x55] 93 1 T52 1 T91 1 T53 1
valid_sources[0x56] 192 1 T98 2 T66 2 T76 2
valid_sources[0x57] 135 1 T155 1 T53 5 T48 1
valid_sources[0x58] 142 1 T152 1 T53 1 T47 2
valid_sources[0x59] 106 1 T53 1 T48 2 T47 1
valid_sources[0x5a] 126 1 T53 1 T84 6 T98 7
valid_sources[0x5b] 60 1 T57 1 T47 1 T98 1
valid_sources[0x5c] 122 1 T121 2 T48 1 T75 1
valid_sources[0x5d] 71 1 T53 2 T73 3 T98 3
valid_sources[0x5e] 77 1 T48 3 T81 2 T47 1
valid_sources[0x5f] 88 1 T144 1 T53 1 T48 1
valid_sources[0x60] 107 1 T19 2 T91 2 T147 2
valid_sources[0x61] 78 1 T53 1 T48 1 T47 1
valid_sources[0x62] 107 1 T53 1 T45 2 T47 1
valid_sources[0x63] 80 1 T151 2 T75 1 T98 4
valid_sources[0x64] 94 1 T53 2 T76 1 T77 1
valid_sources[0x65] 172 1 T156 7 T53 2 T48 2
valid_sources[0x66] 83 1 T59 1 T48 1 T45 4
valid_sources[0x67] 64 1 T48 1 T98 2 T76 2
valid_sources[0x68] 116 1 T53 1 T75 1 T98 3
valid_sources[0x69] 87 1 T53 3 T48 1 T47 1
valid_sources[0x6a] 182 1 T48 1 T47 1 T98 3
valid_sources[0x6b] 91 1 T53 1 T87 3 T73 1
valid_sources[0x6c] 164 1 T53 1 T85 5 T47 2
valid_sources[0x6d] 153 1 T154 2 T53 1 T47 1
valid_sources[0x6e] 91 1 T74 2 T53 1 T82 6
valid_sources[0x6f] 279 1 T121 1 T53 3 T85 3
valid_sources[0x70] 119 1 T121 1 T148 1 T53 3
valid_sources[0x71] 66 1 T146 1 T47 2 T98 2
valid_sources[0x72] 66 1 T151 1 T53 2 T47 1
valid_sources[0x73] 78 1 T53 2 T47 1 T86 1
valid_sources[0x74] 91 1 T47 1 T75 2 T98 4
valid_sources[0x75] 156 1 T82 1 T98 2 T77 2
valid_sources[0x76] 157 1 T48 1 T46 82 T82 1
valid_sources[0x77] 91 1 T4 1 T48 2 T73 1
valid_sources[0x78] 126 1 T85 1 T47 1 T98 3
valid_sources[0x79] 113 1 T52 2 T157 3 T53 1
valid_sources[0x7a] 86 1 T59 1 T144 1 T53 1
valid_sources[0x7b] 73 1 T19 2 T47 2 T73 1
valid_sources[0x7c] 87 1 T75 2 T98 2 T66 1
valid_sources[0x7d] 101 1 T4 1 T49 15 T53 2
valid_sources[0x7e] 105 1 T53 2 T48 1 T82 1
valid_sources[0x7f] 66 1 T53 5 T98 3 T79 3
valid_sources[0x80] 112 1 T142 1 T48 2 T75 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7253 1 T49 23 T50 14 T53 152
values[0x0] all_enables biggest_size 7193 1 T1 1 T42 2 T5 2
values[0x1] all_enables biggest_size 6996 1 T41 2 T42 1 T4 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%