Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 252178 1 T6 35 T7 21 T8 5
full_word 604602 1 T6 10 T7 7 T20 2



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 856430 1 T6 45 T7 28 T20 2
auto[TlIntgErrCmd] 109 1 T45 2 T47 10 T93 3
auto[TlIntgErrData] 123 1 T45 2 T47 7 T93 5
auto[TlIntgErrBoth] 118 1 T45 6 T47 3 T93 2



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 508102 1 T8 10 T17 80 T27 8
auto[1] 348678 1 T6 45 T7 28 T20 2



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 205645 1 T8 4 T27 4 T21 2
auto[TlIntgErrNone] partial auto[1] 46211 1 T6 35 T7 21 T8 1
auto[TlIntgErrNone] full_word auto[0] 302304 1 T8 6 T17 80 T27 4
auto[TlIntgErrNone] full_word auto[1] 302270 1 T6 10 T7 7 T20 2
auto[TlIntgErrCmd] partial auto[0] 44 1 T47 6 T93 1 T80 5
auto[TlIntgErrCmd] partial auto[1] 60 1 T45 2 T47 4 T93 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T93 1 T133 1 T134 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T68 1 T133 1 - -
auto[TlIntgErrData] partial auto[0] 55 1 T45 1 T47 3 T93 1
auto[TlIntgErrData] partial auto[1] 58 1 T47 4 T93 4 T80 1
auto[TlIntgErrData] full_word auto[0] 4 1 T45 1 T128 1 T68 1
auto[TlIntgErrData] full_word auto[1] 6 1 T126 1 T127 1 T132 1
auto[TlIntgErrBoth] partial auto[0] 42 1 T45 2 T80 2 T125 3
auto[TlIntgErrBoth] partial auto[1] 63 1 T45 4 T47 2 T93 2
auto[TlIntgErrBoth] full_word auto[0] 5 1 T125 1 T127 1 T135 1
auto[TlIntgErrBoth] full_word auto[1] 8 1 T47 1 T126 1 T136 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%