SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 25880511 | 14311 | 0 | 0 |
late_debug_enable_rd_A | 25880511 | 6765 | 0 | 0 |
late_debug_enable_regwen_rd_A | 25880511 | 4885 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25880511 | 14311 | 0 | 0 |
T45 | 57892 | 3 | 0 | 0 |
T46 | 44925 | 74 | 0 | 0 |
T47 | 85912 | 5 | 0 | 0 |
T48 | 7310 | 249 | 0 | 0 |
T66 | 449922 | 53 | 0 | 0 |
T73 | 5869 | 361 | 0 | 0 |
T75 | 12339 | 29 | 0 | 0 |
T76 | 7159 | 853 | 0 | 0 |
T77 | 427608 | 82 | 0 | 0 |
T93 | 52815 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25880511 | 6765 | 0 | 0 |
T45 | 57892 | 48 | 0 | 0 |
T48 | 7310 | 84 | 0 | 0 |
T49 | 19854 | 20 | 0 | 0 |
T53 | 328904 | 1040 | 0 | 0 |
T67 | 587225 | 22 | 0 | 0 |
T73 | 5869 | 62 | 0 | 0 |
T75 | 12339 | 64 | 0 | 0 |
T82 | 47258 | 41 | 0 | 0 |
T86 | 5034 | 1 | 0 | 0 |
T115 | 20106 | 19 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 25880511 | 4885 | 0 | 0 |
T45 | 57892 | 43 | 0 | 0 |
T48 | 7310 | 76 | 0 | 0 |
T49 | 19854 | 23 | 0 | 0 |
T67 | 587225 | 28 | 0 | 0 |
T73 | 5869 | 6 | 0 | 0 |
T75 | 12339 | 87 | 0 | 0 |
T82 | 47258 | 36 | 0 | 0 |
T86 | 5034 | 1 | 0 | 0 |
T115 | 20106 | 29 | 0 | 0 |
T120 | 7053 | 12 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |