Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T15

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T15

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8988381	8987573	0	0
selKnown1	9959213	9958405	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8988381	8987573	0	0
T1	358	356	0	0
T2	17390	17388	0	0
T3	3786	3784	0	0
T4	310	308	0	0
T5	310	308	0	0
T7	2	0	0	0
T11	0	16	0	0
T15	0	7	0	0
T19	310	308	0	0
T20	2	0	0	0
T26	11	9	0	0
T30	331304	331302	0	0
T33	0	40	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	42	40	0	0
T39	22	20	0	0
T40	0	40	0	0
T41	348	346	0	0
T42	448	446	0	0
T43	0	8	0	0
T44	314	312	0	0
T54	2	0	0	0
T55	2	0	0	0
T60	0	40	0	0
T62	2	0	0	0
T63	2	0	0	0
T64	2	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	9959213	9958405	0	0
T1	2245	2243	0	0
T2	22137	22135	0	0
T3	6379	6377	0	0
T4	1443	1441	0	0
T5	1262	1260	0	0
T7	2	0	0	0
T11	0	6	0	0
T15	0	2	0	0
T19	3240	3238	0	0
T20	2	0	0	0
T26	10	8	0	0
T30	193524	193522	0	0
T33	0	40	0	0
T38	42	40	0	0
T39	22	20	0	0
T40	0	40	0	0
T41	1504	1502	0	0
T42	1419	1417	0	0
T43	0	4	0	0
T44	1283	1281	0	0
T54	2	0	0	0
T55	2	0	0	0
T60	0	40	0	0
T61	0	40	0	0
T62	2	0	0	0
T63	2	0	0	0
T64	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T15

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T15

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1105586	1105487	0	0
selKnown1	2076527	2076428	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1105586	1105487	0	0
T1	179	178	0	0
T2	8695	8694	0	0
T3	1893	1892	0	0
T4	155	154	0	0
T5	155	154	0	0
T19	155	154	0	0
T30	165652	165651	0	0
T41	174	173	0	0
T42	224	223	0	0
T44	157	156	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2076527	2076428	0	0
T1	2066	2065	0	0
T2	13442	13441	0	0
T3	4486	4485	0	0
T4	1288	1287	0	0
T5	1107	1106	0	0
T19	3085	3084	0	0
T30	27872	27871	0	0
T41	1330	1329	0	0
T42	1195	1194	0	0
T44	1126	1125	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T15

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T15

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	235	136	0	0
selKnown1	224	125	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	235	136	0	0
T7	1	0	0	0
T11	0	8	0	0
T15	0	1	0	0
T20	1	0	0	0
T26	5	4	0	0
T33	0	20	0	0
T38	21	20	0	0
T39	11	10	0	0
T40	0	20	0	0
T43	0	8	0	0
T54	1	0	0	0
T55	1	0	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	1	0	0	0
T63	1	0	0	0
T64	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	224	125	0	0
T7	1	0	0	0
T11	0	3	0	0
T15	0	1	0	0
T20	1	0	0	0
T26	5	4	0	0
T33	0	20	0	0
T38	21	20	0	0
T39	11	10	0	0
T40	0	20	0	0
T43	0	2	0	0
T54	1	0	0	0
T55	1	0	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	1	0	0	0
T63	1	0	0	0
T64	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T15

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T15

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7880953	7880648	0	0
selKnown1	7880953	7880648	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7880953	7880648	0	0
T1	179	178	0	0
T2	8695	8694	0	0
T3	1893	1892	0	0
T4	155	154	0	0
T5	155	154	0	0
T19	155	154	0	0
T30	165652	165651	0	0
T41	174	173	0	0
T42	224	223	0	0
T44	157	156	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	7880953	7880648	0	0
T1	179	178	0	0
T2	8695	8694	0	0
T3	1893	1892	0	0
T4	155	154	0	0
T5	155	154	0	0
T19	155	154	0	0
T30	165652	165651	0	0
T41	174	173	0	0
T42	224	223	0	0
T44	157	156	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T15

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15
1	1	Covered	T15

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1607	1302	0	0
selKnown1	1509	1204	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1302	0	0
T7	1	0	0	0
T11	0	8	0	0
T15	0	6	0	0
T20	1	0	0	0
T26	6	5	0	0
T33	0	20	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	21	20	0	0
T39	11	10	0	0
T40	0	20	0	0
T54	1	0	0	0
T55	1	0	0	0
T60	0	20	0	0
T62	1	0	0	0
T63	1	0	0	0
T64	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509	1204	0	0
T7	1	0	0	0
T11	0	3	0	0
T15	0	1	0	0
T20	1	0	0	0
T26	5	4	0	0
T33	0	20	0	0
T38	21	20	0	0
T39	11	10	0	0
T40	0	20	0	0
T43	0	2	0	0
T54	1	0	0	0
T55	1	0	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	1	0	0	0
T63	1	0	0	0
T64	1	0	0	0