SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 594 | 594 | 0 | 0 |
OutputsKnown_A | 12459162 | 12369612 | 0 | 0 |
gen_flops.OutputDelay_A | 6229581 | 6182790 | 0 | 891 |
gen_no_flops.OutputDelay_A | 6229581 | 6184806 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 594 | 594 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T19 | 6 | 6 | 0 | 0 |
T30 | 6 | 6 | 0 | 0 |
T41 | 6 | 6 | 0 | 0 |
T42 | 6 | 6 | 0 | 0 |
T44 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12459162 | 12369612 | 0 | 0 |
T1 | 12396 | 11958 | 0 | 0 |
T2 | 80652 | 80292 | 0 | 0 |
T3 | 26916 | 26562 | 0 | 0 |
T4 | 7728 | 7332 | 0 | 0 |
T5 | 6642 | 6300 | 0 | 0 |
T19 | 18510 | 18066 | 0 | 0 |
T30 | 167232 | 166788 | 0 | 0 |
T41 | 7980 | 7638 | 0 | 0 |
T42 | 7170 | 6774 | 0 | 0 |
T44 | 6756 | 6324 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 6229581 | 6182790 | 0 | 891 |
T1 | 6198 | 5970 | 0 | 9 |
T2 | 40326 | 40137 | 0 | 9 |
T3 | 13458 | 13272 | 0 | 9 |
T4 | 3864 | 3657 | 0 | 9 |
T5 | 3321 | 3141 | 0 | 9 |
T19 | 9255 | 9024 | 0 | 9 |
T30 | 83616 | 83385 | 0 | 9 |
T41 | 3990 | 3810 | 0 | 9 |
T42 | 3585 | 3378 | 0 | 9 |
T44 | 3378 | 3153 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 6229581 | 6184806 | 0 | 0 |
T1 | 6198 | 5979 | 0 | 0 |
T2 | 40326 | 40146 | 0 | 0 |
T3 | 13458 | 13281 | 0 | 0 |
T4 | 3864 | 3666 | 0 | 0 |
T5 | 3321 | 3150 | 0 | 0 |
T19 | 9255 | 9033 | 0 | 0 |
T30 | 83616 | 83394 | 0 | 0 |
T41 | 3990 | 3819 | 0 | 0 |
T42 | 3585 | 3387 | 0 | 0 |
T44 | 3378 | 3162 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 99 | 99 | 0 | 0 |
OutputsKnown_A | 2076527 | 2061602 | 0 | 0 |
gen_flops.OutputDelay_A | 2076527 | 2060930 | 0 | 297 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99 | 99 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2060930 | 0 | 297 |
T1 | 2066 | 1990 | 0 | 3 |
T2 | 13442 | 13379 | 0 | 3 |
T3 | 4486 | 4424 | 0 | 3 |
T4 | 1288 | 1219 | 0 | 3 |
T5 | 1107 | 1047 | 0 | 3 |
T19 | 3085 | 3008 | 0 | 3 |
T30 | 27872 | 27795 | 0 | 3 |
T41 | 1330 | 1270 | 0 | 3 |
T42 | 1195 | 1126 | 0 | 3 |
T44 | 1126 | 1051 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 99 | 99 | 0 | 0 |
OutputsKnown_A | 2076527 | 2061602 | 0 | 0 |
gen_flops.OutputDelay_A | 2076527 | 2060930 | 0 | 297 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99 | 99 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2060930 | 0 | 297 |
T1 | 2066 | 1990 | 0 | 3 |
T2 | 13442 | 13379 | 0 | 3 |
T3 | 4486 | 4424 | 0 | 3 |
T4 | 1288 | 1219 | 0 | 3 |
T5 | 1107 | 1047 | 0 | 3 |
T19 | 3085 | 3008 | 0 | 3 |
T30 | 27872 | 27795 | 0 | 3 |
T41 | 1330 | 1270 | 0 | 3 |
T42 | 1195 | 1126 | 0 | 3 |
T44 | 1126 | 1051 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 99 | 99 | 0 | 0 |
OutputsKnown_A | 2076527 | 2061602 | 0 | 0 |
gen_no_flops.OutputDelay_A | 2076527 | 2061602 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99 | 99 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 99 | 99 | 0 | 0 |
OutputsKnown_A | 2076527 | 2061602 | 0 | 0 |
gen_flops.OutputDelay_A | 2076527 | 2060930 | 0 | 297 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99 | 99 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2060930 | 0 | 297 |
T1 | 2066 | 1990 | 0 | 3 |
T2 | 13442 | 13379 | 0 | 3 |
T3 | 4486 | 4424 | 0 | 3 |
T4 | 1288 | 1219 | 0 | 3 |
T5 | 1107 | 1047 | 0 | 3 |
T19 | 3085 | 3008 | 0 | 3 |
T30 | 27872 | 27795 | 0 | 3 |
T41 | 1330 | 1270 | 0 | 3 |
T42 | 1195 | 1126 | 0 | 3 |
T44 | 1126 | 1051 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 99 | 99 | 0 | 0 |
OutputsKnown_A | 2076527 | 2061602 | 0 | 0 |
gen_no_flops.OutputDelay_A | 2076527 | 2061602 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99 | 99 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 99 | 99 | 0 | 0 |
OutputsKnown_A | 2076527 | 2061602 | 0 | 0 |
gen_no_flops.OutputDelay_A | 2076527 | 2061602 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 99 | 99 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
T42 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2076527 | 2061602 | 0 | 0 |
T1 | 2066 | 1993 | 0 | 0 |
T2 | 13442 | 13382 | 0 | 0 |
T3 | 4486 | 4427 | 0 | 0 |
T4 | 1288 | 1222 | 0 | 0 |
T5 | 1107 | 1050 | 0 | 0 |
T19 | 3085 | 3011 | 0 | 0 |
T30 | 27872 | 27798 | 0 | 0 |
T41 | 1330 | 1273 | 0 | 0 |
T42 | 1195 | 1129 | 0 | 0 |
T44 | 1126 | 1054 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |