Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_rsp_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T41,*T5,*T44 Yes T1,T41,T5 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T1,T41,T42 Yes T41,T4,T5 INPUT
data_o[56:0] Yes Yes T41,T5,T44 Yes T1,T41,T5 OUTPUT
syndrome_o[6:0] Yes Yes T41,T5,T44 Yes T1,T41,T4 OUTPUT
err_o[1:0] Yes Yes T41,T5,T19 Yes T41,T5,T44 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 260 156 60.00
Total Bits 0->1 130 78 60.00
Total Bits 1->0 130 78 60.00

Ports 4 2 50.00
Port Bits 260 156 60.00
Port Bits 0->1 130 78 60.00
Port Bits 1->0 130 78 60.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[5:0] Yes Yes *T41,*T30,*T8 Yes T30,T33,T34 INPUT
data_i[56:6] No No No INPUT
data_i[63:57] Yes Yes T30,T32,T33 Yes T30,T54,T51 INPUT
data_o[55:0] Yes Yes *T41,*T30,*T8 Yes T30,T33,T34 OUTPUT
data_o[56] No No No OUTPUT
syndrome_o[6:0] Yes Yes T30,T33,T34 Yes T41,T30,T8 OUTPUT
err_o[1:0] Yes Yes T30,T33,T34 Yes T41,T30,T8 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T41,*T5,*T44 Yes T41,T5,T44 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T1,T41,T42 Yes T41,T4,T5 INPUT
data_o[56:0] Yes Yes T41,T5,T44 Yes T41,T5,T44 OUTPUT
syndrome_o[6:0] Yes Yes T41,T5,T44 Yes T41,T5,T44 OUTPUT
err_o[1:0] Yes Yes T41,T5,T44 Yes T41,T5,T44 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T39,*T7,*T8 Yes T1,T6,T39 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T6,T39,T7 Yes T19,T6,T39 INPUT
data_o[56:0] Yes Yes T39,T7,T8 Yes T1,T6,T39 OUTPUT
syndrome_o[6:0] Yes Yes T39,T7,T14 Yes T1,T4,T39 OUTPUT
err_o[1:0] Yes Yes T5,T19,T6 Yes T39,T7,T14 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%