Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.37 93.86 81.46 87.61 74.36 82.33 98.42 37.55


Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T258 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.260068272 Apr 30 02:58:52 PM PDT 24 Apr 30 02:59:15 PM PDT 24 6017280712 ps
T259 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1717626540 Apr 30 02:58:04 PM PDT 24 Apr 30 02:58:07 PM PDT 24 127705767 ps
T124 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.468321112 Apr 30 02:58:01 PM PDT 24 Apr 30 02:58:10 PM PDT 24 341643762 ps
T260 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.539065532 Apr 30 02:57:15 PM PDT 24 Apr 30 02:57:17 PM PDT 24 92862986 ps
T261 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.763978758 Apr 30 02:58:04 PM PDT 24 Apr 30 02:58:07 PM PDT 24 1376183295 ps
T262 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3762796362 Apr 30 02:57:22 PM PDT 24 Apr 30 02:57:29 PM PDT 24 892506938 ps
T263 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4022522695 Apr 30 02:57:25 PM PDT 24 Apr 30 02:57:29 PM PDT 24 929413847 ps
T264 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3764455947 Apr 30 02:58:43 PM PDT 24 Apr 30 02:58:45 PM PDT 24 67522433 ps
T265 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.121745531 Apr 30 02:57:49 PM PDT 24 Apr 30 02:57:56 PM PDT 24 233998129 ps
T266 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2078525523 Apr 30 02:58:31 PM PDT 24 Apr 30 02:58:33 PM PDT 24 91604485 ps
T128 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4122927760 Apr 30 02:58:16 PM PDT 24 Apr 30 02:58:40 PM PDT 24 1237273870 ps
T267 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1924255622 Apr 30 02:56:54 PM PDT 24 Apr 30 02:57:08 PM PDT 24 9236508752 ps
T268 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.1349340030 Apr 30 02:58:52 PM PDT 24 Apr 30 02:59:25 PM PDT 24 18274974439 ps
T269 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1201401086 Apr 30 02:58:34 PM PDT 24 Apr 30 02:58:36 PM PDT 24 439877407 ps
T270 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2263569192 Apr 30 02:57:32 PM PDT 24 Apr 30 02:57:33 PM PDT 24 34272785 ps
T271 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.671140543 Apr 30 02:57:35 PM PDT 24 Apr 30 02:57:37 PM PDT 24 74694812 ps
T272 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3456864411 Apr 30 02:58:11 PM PDT 24 Apr 30 02:58:18 PM PDT 24 142786071 ps
T273 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4000994235 Apr 30 02:58:17 PM PDT 24 Apr 30 02:58:20 PM PDT 24 144243055 ps
T274 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2854726420 Apr 30 02:57:00 PM PDT 24 Apr 30 02:58:05 PM PDT 24 2135966504 ps
T275 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1194429198 Apr 30 02:57:32 PM PDT 24 Apr 30 02:58:13 PM PDT 24 14958591124 ps
T276 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.2757073704 Apr 30 02:58:49 PM PDT 24 Apr 30 02:59:40 PM PDT 24 17525162065 ps
T127 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1502337001 Apr 30 02:58:37 PM PDT 24 Apr 30 02:58:57 PM PDT 24 2371177301 ps
T277 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3040417886 Apr 30 02:56:59 PM PDT 24 Apr 30 02:57:01 PM PDT 24 33878625 ps
T278 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3123125548 Apr 30 02:57:04 PM PDT 24 Apr 30 02:57:25 PM PDT 24 1483947935 ps
T279 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3129015611 Apr 30 02:58:27 PM PDT 24 Apr 30 02:58:30 PM PDT 24 534269194 ps
T56 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1433882009 Apr 30 02:57:06 PM PDT 24 Apr 30 02:57:08 PM PDT 24 652351097 ps
T57 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.315378249 Apr 30 02:57:59 PM PDT 24 Apr 30 02:58:00 PM PDT 24 225897060 ps
T280 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.255423822 Apr 30 02:57:45 PM PDT 24 Apr 30 02:57:49 PM PDT 24 324113875 ps
T281 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3782278860 Apr 30 02:57:24 PM PDT 24 Apr 30 02:57:27 PM PDT 24 61456435 ps
T282 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4198169375 Apr 30 02:56:52 PM PDT 24 Apr 30 02:56:53 PM PDT 24 37319413 ps
T283 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1941457809 Apr 30 02:58:42 PM PDT 24 Apr 30 02:58:47 PM PDT 24 76774550 ps
T284 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.399704188 Apr 30 02:57:33 PM PDT 24 Apr 30 02:57:34 PM PDT 24 94152437 ps
T285 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3701500247 Apr 30 02:57:38 PM PDT 24 Apr 30 02:57:39 PM PDT 24 54041352 ps
T286 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.739516736 Apr 30 02:57:32 PM PDT 24 Apr 30 02:57:34 PM PDT 24 64257227 ps
T287 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1554913804 Apr 30 02:57:07 PM PDT 24 Apr 30 02:57:08 PM PDT 24 72462562 ps
T288 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2545569012 Apr 30 02:57:45 PM PDT 24 Apr 30 02:57:48 PM PDT 24 95435303 ps
T289 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3907466865 Apr 30 02:56:56 PM PDT 24 Apr 30 02:56:57 PM PDT 24 41822130 ps
T290 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1884448482 Apr 30 02:58:09 PM PDT 24 Apr 30 02:58:12 PM PDT 24 106895657 ps
T291 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.413715667 Apr 30 02:58:33 PM PDT 24 Apr 30 02:58:53 PM PDT 24 10366829971 ps
T292 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1852163635 Apr 30 02:58:23 PM PDT 24 Apr 30 02:58:24 PM PDT 24 212183736 ps
T293 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2118283587 Apr 30 02:57:25 PM PDT 24 Apr 30 02:57:27 PM PDT 24 41079444 ps
T294 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1056195847 Apr 30 02:58:29 PM PDT 24 Apr 30 02:58:33 PM PDT 24 94913824 ps
T295 /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.8471738 Apr 30 02:58:49 PM PDT 24 Apr 30 02:59:18 PM PDT 24 28997514498 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2126938993 Apr 30 02:57:31 PM PDT 24 Apr 30 02:58:01 PM PDT 24 1145737667 ps
T297 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2778567079 Apr 30 02:56:48 PM PDT 24 Apr 30 02:57:54 PM PDT 24 2188853104 ps
T298 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.573093058 Apr 30 02:58:41 PM PDT 24 Apr 30 02:58:43 PM PDT 24 51061212 ps
T299 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2915535749 Apr 30 02:57:29 PM PDT 24 Apr 30 02:58:05 PM PDT 24 2581424025 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.106222132 Apr 30 02:57:38 PM PDT 24 Apr 30 02:58:04 PM PDT 24 9017354226 ps
T301 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2697700368 Apr 30 02:58:42 PM PDT 24 Apr 30 02:58:44 PM PDT 24 114017899 ps
T302 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.566391925 Apr 30 02:58:36 PM PDT 24 Apr 30 02:58:40 PM PDT 24 147958934 ps
T303 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1696220995 Apr 30 02:58:28 PM PDT 24 Apr 30 02:58:32 PM PDT 24 38371710 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3692475579 Apr 30 02:57:46 PM PDT 24 Apr 30 02:58:08 PM PDT 24 2197270372 ps
T305 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3100572022 Apr 30 02:58:25 PM PDT 24 Apr 30 02:58:29 PM PDT 24 285876107 ps
T107 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2541124437 Apr 30 02:58:33 PM PDT 24 Apr 30 02:58:36 PM PDT 24 44413093 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.55937359 Apr 30 02:57:49 PM PDT 24 Apr 30 02:57:50 PM PDT 24 51601133 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2257270662 Apr 30 02:57:22 PM PDT 24 Apr 30 02:58:03 PM PDT 24 18009126659 ps
T308 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3720783203 Apr 30 02:58:06 PM PDT 24 Apr 30 02:58:25 PM PDT 24 901684597 ps
T92 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.227563944 Apr 30 02:57:35 PM PDT 24 Apr 30 02:57:37 PM PDT 24 455166954 ps
T309 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1541878325 Apr 30 02:58:28 PM PDT 24 Apr 30 02:58:32 PM PDT 24 1451951504 ps
T310 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2034155005 Apr 30 02:58:19 PM PDT 24 Apr 30 02:58:22 PM PDT 24 468755196 ps

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2329456451
Short name T16
Test name
Test status
Simulation time 1381938166 ps
CPU time 2.8 seconds
Started Apr 30 02:40:47 PM PDT 24
Finished Apr 30 02:40:50 PM PDT 24
Peak memory 205300 kb
Host smart-39c28c03-9260-40d3-8669-b1a3cb605fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329456451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2329456451
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.403621331
Short name T5
Test name
Test status
Simulation time 5064820882 ps
CPU time 5.71 seconds
Started Apr 30 02:41:34 PM PDT 24
Finished Apr 30 02:41:40 PM PDT 24
Peak memory 205456 kb
Host smart-1c79f70e-b7bf-493c-a825-98c8ff010619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403621331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.403621331
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3856646932
Short name T42
Test name
Test status
Simulation time 11632492346 ps
CPU time 42.04 seconds
Started Apr 30 02:57:36 PM PDT 24
Finished Apr 30 02:58:19 PM PDT 24
Peak memory 221336 kb
Host smart-14f58271-6f2a-4003-a4f5-7b7778d5f2c8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856646932 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3856646932
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.18143515
Short name T30
Test name
Test status
Simulation time 4357543571 ps
CPU time 7.38 seconds
Started Apr 30 02:41:03 PM PDT 24
Finished Apr 30 02:41:11 PM PDT 24
Peak memory 205616 kb
Host smart-e8238f1b-ec9a-4950-8c78-b6541309872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18143515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.18143515
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.446693040
Short name T38
Test name
Test status
Simulation time 19828943 ps
CPU time 0.75 seconds
Started Apr 30 02:41:11 PM PDT 24
Finished Apr 30 02:41:12 PM PDT 24
Peak memory 205136 kb
Host smart-93f6532d-8959-4786-865b-5742bd871edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446693040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.446693040
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1352652927
Short name T131
Test name
Test status
Simulation time 3194654737 ps
CPU time 6.07 seconds
Started Apr 30 02:41:44 PM PDT 24
Finished Apr 30 02:41:50 PM PDT 24
Peak memory 205420 kb
Host smart-fcb63d65-d4e6-43a8-b1a5-31a70dfb3302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352652927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1352652927
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.70280447
Short name T66
Test name
Test status
Simulation time 534254584 ps
CPU time 11.62 seconds
Started Apr 30 02:58:22 PM PDT 24
Finished Apr 30 02:58:34 PM PDT 24
Peak memory 221580 kb
Host smart-f8a71603-2f1f-4a6d-8f9d-fdb49a5fede5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70280447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.70280447
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1644723643
Short name T6
Test name
Test status
Simulation time 1568464423 ps
CPU time 6.53 seconds
Started Apr 30 02:41:12 PM PDT 24
Finished Apr 30 02:41:19 PM PDT 24
Peak memory 205400 kb
Host smart-a548d2c0-1298-42c3-8fb3-3b6fe1843731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644723643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1644723643
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.78029018
Short name T83
Test name
Test status
Simulation time 1473936016 ps
CPU time 59.06 seconds
Started Apr 30 02:57:13 PM PDT 24
Finished Apr 30 02:58:13 PM PDT 24
Peak memory 205080 kb
Host smart-48932981-8845-451b-8da0-7f5c80369acd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78029018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.78029018
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1502337001
Short name T127
Test name
Test status
Simulation time 2371177301 ps
CPU time 19.03 seconds
Started Apr 30 02:58:37 PM PDT 24
Finished Apr 30 02:58:57 PM PDT 24
Peak memory 221304 kb
Host smart-2f9f7491-9783-459f-836b-d6ff4129525b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502337001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
502337001
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1331964596
Short name T33
Test name
Test status
Simulation time 193321556 ps
CPU time 1.29 seconds
Started Apr 30 02:40:58 PM PDT 24
Finished Apr 30 02:41:00 PM PDT 24
Peak memory 229388 kb
Host smart-560eb6f5-2747-49a0-9a52-2188e0719e9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331964596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1331964596
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1637394549
Short name T24
Test name
Test status
Simulation time 99617377 ps
CPU time 0.89 seconds
Started Apr 30 02:40:51 PM PDT 24
Finished Apr 30 02:40:53 PM PDT 24
Peak memory 205164 kb
Host smart-ba02f303-6d58-428e-b952-f3ebcbb07498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637394549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1637394549
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1989074383
Short name T96
Test name
Test status
Simulation time 483242943 ps
CPU time 2.51 seconds
Started Apr 30 02:57:20 PM PDT 24
Finished Apr 30 02:57:23 PM PDT 24
Peak memory 213104 kb
Host smart-40427838-12c1-4c8b-bdd5-32ba079565fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989074383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1989074383
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3372691395
Short name T62
Test name
Test status
Simulation time 1082100612 ps
CPU time 20.43 seconds
Started Apr 30 02:57:25 PM PDT 24
Finished Apr 30 02:57:46 PM PDT 24
Peak memory 221208 kb
Host smart-ce1828bc-cad4-4011-ab66-f2651666f997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372691395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3372691395
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1829060189
Short name T12
Test name
Test status
Simulation time 47981924 ps
CPU time 0.76 seconds
Started Apr 30 02:40:55 PM PDT 24
Finished Apr 30 02:40:57 PM PDT 24
Peak memory 205132 kb
Host smart-31ef4de5-67c6-499d-8e98-3f0f63d3eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829060189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1829060189
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.711495269
Short name T15
Test name
Test status
Simulation time 108808908 ps
CPU time 0.77 seconds
Started Apr 30 02:40:48 PM PDT 24
Finished Apr 30 02:40:49 PM PDT 24
Peak memory 213348 kb
Host smart-18de0832-947e-49f6-a6cb-eb26089b6200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711495269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.711495269
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3485693487
Short name T23
Test name
Test status
Simulation time 2183158772 ps
CPU time 1.32 seconds
Started Apr 30 02:40:48 PM PDT 24
Finished Apr 30 02:40:49 PM PDT 24
Peak memory 205528 kb
Host smart-50b02dbc-b163-4401-b334-b41b1fe6026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485693487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3485693487
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.803977138
Short name T35
Test name
Test status
Simulation time 31540043 ps
CPU time 0.72 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:56 PM PDT 24
Peak memory 205188 kb
Host smart-19146307-f2d2-4d03-905b-9c172835349c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803977138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.803977138
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.262962356
Short name T28
Test name
Test status
Simulation time 1245635401 ps
CPU time 2.34 seconds
Started Apr 30 02:41:12 PM PDT 24
Finished Apr 30 02:41:14 PM PDT 24
Peak memory 205448 kb
Host smart-4a09f41a-2fe5-4c49-9688-6de87d54b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262962356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.262962356
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.194171163
Short name T19
Test name
Test status
Simulation time 85902358 ps
CPU time 0.71 seconds
Started Apr 30 02:40:49 PM PDT 24
Finished Apr 30 02:40:50 PM PDT 24
Peak memory 205136 kb
Host smart-10c3106f-2941-4b41-9a25-ffa04a72e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194171163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.194171163
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.1349340030
Short name T268
Test name
Test status
Simulation time 18274974439 ps
CPU time 32.49 seconds
Started Apr 30 02:58:52 PM PDT 24
Finished Apr 30 02:59:25 PM PDT 24
Peak memory 221364 kb
Host smart-4a22ab4d-b979-4053-8414-7725bed0a682
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349340030 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.1349340030
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3683140563
Short name T112
Test name
Test status
Simulation time 6590914625 ps
CPU time 25.86 seconds
Started Apr 30 02:58:18 PM PDT 24
Finished Apr 30 02:58:44 PM PDT 24
Peak memory 214700 kb
Host smart-c2718f50-e5a2-4f7e-8b8d-7a6b61c2b1d9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683140563 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.3683140563
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4220070028
Short name T175
Test name
Test status
Simulation time 74245507 ps
CPU time 0.88 seconds
Started Apr 30 02:56:58 PM PDT 24
Finished Apr 30 02:56:59 PM PDT 24
Peak memory 204888 kb
Host smart-6cf07035-7569-4f66-8b2a-aac0b2dcf1a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220070028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.4220070028
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1433882009
Short name T56
Test name
Test status
Simulation time 652351097 ps
CPU time 1.6 seconds
Started Apr 30 02:57:06 PM PDT 24
Finished Apr 30 02:57:08 PM PDT 24
Peak memory 204800 kb
Host smart-90698408-8b88-432d-8c82-c324836f0230
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433882009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
433882009
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1922841563
Short name T89
Test name
Test status
Simulation time 568758285 ps
CPU time 2.89 seconds
Started Apr 30 02:57:29 PM PDT 24
Finished Apr 30 02:57:32 PM PDT 24
Peak memory 204884 kb
Host smart-0b6bfa48-0053-4495-b824-5fcfe1541c12
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922841563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1922841563
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2985712010
Short name T82
Test name
Test status
Simulation time 4295165521 ps
CPU time 7.65 seconds
Started Apr 30 02:57:51 PM PDT 24
Finished Apr 30 02:57:59 PM PDT 24
Peak memory 204924 kb
Host smart-a365c869-052d-429a-afcc-acbbdf3834ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985712010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2985712010
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1342804725
Short name T63
Test name
Test status
Simulation time 3741086066 ps
CPU time 19.45 seconds
Started Apr 30 02:58:19 PM PDT 24
Finished Apr 30 02:58:39 PM PDT 24
Peak memory 221212 kb
Host smart-db9bb08d-03ed-4c8f-b48c-4acd97eecf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342804725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
342804725
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3918933763
Short name T45
Test name
Test status
Simulation time 52993292 ps
CPU time 0.75 seconds
Started Apr 30 02:41:34 PM PDT 24
Finished Apr 30 02:41:35 PM PDT 24
Peak memory 205152 kb
Host smart-6314e3a4-1b5e-4c54-a408-8517259e7bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918933763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3918933763
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1857219777
Short name T8
Test name
Test status
Simulation time 367647750 ps
CPU time 1.05 seconds
Started Apr 30 02:40:52 PM PDT 24
Finished Apr 30 02:40:53 PM PDT 24
Peak memory 204992 kb
Host smart-a938143a-1870-4e9c-b44d-609e0d8ec085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857219777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1857219777
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1114402361
Short name T153
Test name
Test status
Simulation time 10258421929 ps
CPU time 20 seconds
Started Apr 30 02:58:07 PM PDT 24
Finished Apr 30 02:58:28 PM PDT 24
Peak memory 214936 kb
Host smart-fa72c544-971e-47f2-af48-3ed8d6f3980b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114402361 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.1114402361
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3133857434
Short name T40
Test name
Test status
Simulation time 832112148 ps
CPU time 8.87 seconds
Started Apr 30 02:58:40 PM PDT 24
Finished Apr 30 02:58:49 PM PDT 24
Peak memory 221308 kb
Host smart-0d0121e2-cb81-48f9-9d00-1d485cd77111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133857434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
133857434
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.449538944
Short name T123
Test name
Test status
Simulation time 237087419 ps
CPU time 8.69 seconds
Started Apr 30 02:57:48 PM PDT 24
Finished Apr 30 02:57:57 PM PDT 24
Peak memory 213124 kb
Host smart-e98cad6d-68b7-41ac-af9b-5efbf213940d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449538944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.449538944
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3994505994
Short name T126
Test name
Test status
Simulation time 2834387252 ps
CPU time 16.42 seconds
Started Apr 30 02:57:30 PM PDT 24
Finished Apr 30 02:57:46 PM PDT 24
Peak memory 221316 kb
Host smart-9888d85b-bcd8-4fa7-ba6c-5c27cd43e62c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994505994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3994505994
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2996097866
Short name T182
Test name
Test status
Simulation time 20116345930 ps
CPU time 14.43 seconds
Started Apr 30 02:57:31 PM PDT 24
Finished Apr 30 02:57:46 PM PDT 24
Peak memory 215704 kb
Host smart-b3bf7e3d-16f5-4c53-9cc5-13ecdf627683
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996097866 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2996097866
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2778567079
Short name T297
Test name
Test status
Simulation time 2188853104 ps
CPU time 65.73 seconds
Started Apr 30 02:56:48 PM PDT 24
Finished Apr 30 02:57:54 PM PDT 24
Peak memory 216956 kb
Host smart-6456e7b1-3ae0-40d3-ad3a-837d7c649978
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778567079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2778567079
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2757624322
Short name T88
Test name
Test status
Simulation time 1443933706 ps
CPU time 56.81 seconds
Started Apr 30 02:57:03 PM PDT 24
Finished Apr 30 02:58:01 PM PDT 24
Peak memory 204996 kb
Host smart-c57612a1-49ad-4fca-813f-b58094d4a4cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757624322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2757624322
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3040417886
Short name T277
Test name
Test status
Simulation time 33878625 ps
CPU time 1.57 seconds
Started Apr 30 02:56:59 PM PDT 24
Finished Apr 30 02:57:01 PM PDT 24
Peak memory 213036 kb
Host smart-09ffea6e-f097-4c8c-a8ae-51acf7d7e010
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040417886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3040417886
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3469485646
Short name T77
Test name
Test status
Simulation time 131812244 ps
CPU time 2.4 seconds
Started Apr 30 02:57:00 PM PDT 24
Finished Apr 30 02:57:04 PM PDT 24
Peak memory 216884 kb
Host smart-f9f11d24-63c3-4eb7-b1c8-8c6908dccc92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469485646 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3469485646
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.220431588
Short name T93
Test name
Test status
Simulation time 1294209815 ps
CPU time 2.78 seconds
Started Apr 30 02:57:01 PM PDT 24
Finished Apr 30 02:57:05 PM PDT 24
Peak memory 213108 kb
Host smart-ba368e04-afcc-4db8-8307-e840fbe42b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220431588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.220431588
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1924255622
Short name T267
Test name
Test status
Simulation time 9236508752 ps
CPU time 13.48 seconds
Started Apr 30 02:56:54 PM PDT 24
Finished Apr 30 02:57:08 PM PDT 24
Peak memory 204836 kb
Host smart-7d1a799d-626c-4bbc-9818-ce68c5e23e7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924255622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1924255622
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3482215925
Short name T91
Test name
Test status
Simulation time 740946795 ps
CPU time 3.39 seconds
Started Apr 30 02:56:54 PM PDT 24
Finished Apr 30 02:56:58 PM PDT 24
Peak memory 204812 kb
Host smart-d41bbaaf-dd26-4950-8898-87651653db3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482215925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3482215925
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.255891288
Short name T215
Test name
Test status
Simulation time 1000396385 ps
CPU time 4.22 seconds
Started Apr 30 02:56:57 PM PDT 24
Finished Apr 30 02:57:02 PM PDT 24
Peak memory 205080 kb
Host smart-712b686e-8cff-43c9-9e89-bc1b13ff157e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255891288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.255891288
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3907466865
Short name T289
Test name
Test status
Simulation time 41822130 ps
CPU time 0.79 seconds
Started Apr 30 02:56:56 PM PDT 24
Finished Apr 30 02:56:57 PM PDT 24
Peak memory 204640 kb
Host smart-cea980e9-4f82-46bb-904b-21572d211000
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907466865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3907466865
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.312404437
Short name T234
Test name
Test status
Simulation time 1801503751 ps
CPU time 3.14 seconds
Started Apr 30 02:56:57 PM PDT 24
Finished Apr 30 02:57:01 PM PDT 24
Peak memory 204800 kb
Host smart-8095491a-74b5-429d-88f4-f69b919dc28e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312404437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.312404437
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4198169375
Short name T282
Test name
Test status
Simulation time 37319413 ps
CPU time 0.7 seconds
Started Apr 30 02:56:52 PM PDT 24
Finished Apr 30 02:56:53 PM PDT 24
Peak memory 204604 kb
Host smart-d72cc303-772a-48df-885d-16be90745c90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198169375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
198169375
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4148499664
Short name T191
Test name
Test status
Simulation time 69647237 ps
CPU time 0.66 seconds
Started Apr 30 02:57:00 PM PDT 24
Finished Apr 30 02:57:01 PM PDT 24
Peak memory 204612 kb
Host smart-1ace0dc6-2488-4801-8762-cfb9e42229db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148499664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4148499664
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2256828654
Short name T218
Test name
Test status
Simulation time 19156393 ps
CPU time 0.72 seconds
Started Apr 30 02:57:01 PM PDT 24
Finished Apr 30 02:57:02 PM PDT 24
Peak memory 204544 kb
Host smart-7c9a7d99-b9cf-4a0b-b6df-ba723bdd7ce4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256828654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2256828654
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3356848573
Short name T98
Test name
Test status
Simulation time 829293201 ps
CPU time 4.66 seconds
Started Apr 30 02:57:01 PM PDT 24
Finished Apr 30 02:57:06 PM PDT 24
Peak memory 204888 kb
Host smart-32597301-fdef-4960-ab01-0413af87a372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356848573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3356848573
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2169412101
Short name T240
Test name
Test status
Simulation time 100241705 ps
CPU time 3.43 seconds
Started Apr 30 02:57:00 PM PDT 24
Finished Apr 30 02:57:05 PM PDT 24
Peak memory 215732 kb
Host smart-7878dfda-8e12-44a0-899d-ba00e8b7c48a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169412101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2169412101
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3123125548
Short name T278
Test name
Test status
Simulation time 1483947935 ps
CPU time 20.32 seconds
Started Apr 30 02:57:04 PM PDT 24
Finished Apr 30 02:57:25 PM PDT 24
Peak memory 221356 kb
Host smart-232a6e59-8c39-4d94-ba94-e549a2a97c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123125548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3123125548
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2854726420
Short name T274
Test name
Test status
Simulation time 2135966504 ps
CPU time 64.44 seconds
Started Apr 30 02:57:00 PM PDT 24
Finished Apr 30 02:58:05 PM PDT 24
Peak memory 204832 kb
Host smart-c5108d27-6897-40ac-a371-30c63d6fca46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854726420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2854726420
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.417336092
Short name T219
Test name
Test status
Simulation time 1017143804 ps
CPU time 4.58 seconds
Started Apr 30 02:57:16 PM PDT 24
Finished Apr 30 02:57:21 PM PDT 24
Peak memory 218260 kb
Host smart-e941e8d2-5d2c-4b9a-8782-06d3a9e61a60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417336092 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.417336092
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1569995202
Short name T221
Test name
Test status
Simulation time 214105860 ps
CPU time 1.49 seconds
Started Apr 30 02:57:15 PM PDT 24
Finished Apr 30 02:57:17 PM PDT 24
Peak memory 213084 kb
Host smart-271e8963-6b2f-4682-9bfa-a067df9137f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569995202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1569995202
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2002212428
Short name T186
Test name
Test status
Simulation time 18489136779 ps
CPU time 62.06 seconds
Started Apr 30 02:57:08 PM PDT 24
Finished Apr 30 02:58:10 PM PDT 24
Peak memory 204892 kb
Host smart-2403a5f3-0e6f-4b46-9633-294140741183
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002212428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2002212428
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2298716815
Short name T213
Test name
Test status
Simulation time 19183614352 ps
CPU time 65.55 seconds
Started Apr 30 02:57:12 PM PDT 24
Finished Apr 30 02:58:18 PM PDT 24
Peak memory 204956 kb
Host smart-6b974812-8f55-476c-a75c-f8baaacea98a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298716815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2298716815
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.799762205
Short name T90
Test name
Test status
Simulation time 3250263054 ps
CPU time 3.83 seconds
Started Apr 30 02:57:08 PM PDT 24
Finished Apr 30 02:57:12 PM PDT 24
Peak memory 204940 kb
Host smart-62c5c75a-e9ba-4656-894a-26402100696d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799762205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.799762205
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3408804396
Short name T58
Test name
Test status
Simulation time 78720300 ps
CPU time 0.79 seconds
Started Apr 30 02:57:08 PM PDT 24
Finished Apr 30 02:57:09 PM PDT 24
Peak memory 204620 kb
Host smart-d42e5013-c57e-4709-b55d-2f3de8168b8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408804396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3408804396
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.708597091
Short name T181
Test name
Test status
Simulation time 506156235 ps
CPU time 2.03 seconds
Started Apr 30 02:57:09 PM PDT 24
Finished Apr 30 02:57:11 PM PDT 24
Peak memory 204808 kb
Host smart-619e55e4-3903-4a0d-8abd-d9bd9b6a696a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708597091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.708597091
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1907597636
Short name T183
Test name
Test status
Simulation time 164891117 ps
CPU time 0.79 seconds
Started Apr 30 02:57:11 PM PDT 24
Finished Apr 30 02:57:12 PM PDT 24
Peak memory 204616 kb
Host smart-ecc04ef8-8b0a-402e-9054-aab10417cfcb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907597636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1907597636
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1554913804
Short name T287
Test name
Test status
Simulation time 72462562 ps
CPU time 0.74 seconds
Started Apr 30 02:57:07 PM PDT 24
Finished Apr 30 02:57:08 PM PDT 24
Peak memory 204536 kb
Host smart-5987386f-9321-4867-a5a8-08a2763625e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554913804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
554913804
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2057548654
Short name T226
Test name
Test status
Simulation time 65438193 ps
CPU time 0.69 seconds
Started Apr 30 02:57:17 PM PDT 24
Finished Apr 30 02:57:18 PM PDT 24
Peak memory 204624 kb
Host smart-568d7640-44b6-488d-aad7-1d4fecb0ce2c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057548654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2057548654
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.539065532
Short name T260
Test name
Test status
Simulation time 92862986 ps
CPU time 0.69 seconds
Started Apr 30 02:57:15 PM PDT 24
Finished Apr 30 02:57:17 PM PDT 24
Peak memory 204596 kb
Host smart-4ecb08f2-e147-4ca8-b488-bc5d352e2fc3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539065532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.539065532
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.863400866
Short name T101
Test name
Test status
Simulation time 422496236 ps
CPU time 4.22 seconds
Started Apr 30 02:57:16 PM PDT 24
Finished Apr 30 02:57:21 PM PDT 24
Peak memory 204904 kb
Host smart-36e7b1ca-e9d6-4305-b50b-fc6d0ced336a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863400866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.863400866
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1264796661
Short name T224
Test name
Test status
Simulation time 319502813 ps
CPU time 5.54 seconds
Started Apr 30 02:57:07 PM PDT 24
Finished Apr 30 02:57:13 PM PDT 24
Peak memory 213164 kb
Host smart-e7d09c9a-406f-422f-b531-6c525cbe01a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264796661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1264796661
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3476188674
Short name T125
Test name
Test status
Simulation time 409202939 ps
CPU time 9.07 seconds
Started Apr 30 02:57:09 PM PDT 24
Finished Apr 30 02:57:18 PM PDT 24
Peak memory 213152 kb
Host smart-4959266a-0db0-4041-8e74-8ef3647f94ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476188674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3476188674
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3933400761
Short name T207
Test name
Test status
Simulation time 136362737 ps
CPU time 3.49 seconds
Started Apr 30 02:58:18 PM PDT 24
Finished Apr 30 02:58:22 PM PDT 24
Peak memory 218028 kb
Host smart-ffdd123d-e357-4d40-8b37-b83667edcf82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933400761 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3933400761
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1884448482
Short name T290
Test name
Test status
Simulation time 106895657 ps
CPU time 2.45 seconds
Started Apr 30 02:58:09 PM PDT 24
Finished Apr 30 02:58:12 PM PDT 24
Peak memory 213152 kb
Host smart-5b741139-b89c-4f57-8ec3-9ae00523d940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884448482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1884448482
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3856420998
Short name T225
Test name
Test status
Simulation time 430251846 ps
CPU time 2.27 seconds
Started Apr 30 02:58:06 PM PDT 24
Finished Apr 30 02:58:09 PM PDT 24
Peak memory 204852 kb
Host smart-cca26bc2-848c-42bf-8ac7-6de235616ad7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856420998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3856420998
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2967538379
Short name T174
Test name
Test status
Simulation time 154801097 ps
CPU time 0.83 seconds
Started Apr 30 02:58:06 PM PDT 24
Finished Apr 30 02:58:08 PM PDT 24
Peak memory 204548 kb
Host smart-5d9dbcc0-ea25-4cb2-94dc-f07fb374036e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967538379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2967538379
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.513433089
Short name T102
Test name
Test status
Simulation time 149784301 ps
CPU time 6.2 seconds
Started Apr 30 02:58:06 PM PDT 24
Finished Apr 30 02:58:12 PM PDT 24
Peak memory 204904 kb
Host smart-11cf67b0-7b97-4372-ae75-77789905d6be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513433089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.513433089
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1717626540
Short name T259
Test name
Test status
Simulation time 127705767 ps
CPU time 2.3 seconds
Started Apr 30 02:58:04 PM PDT 24
Finished Apr 30 02:58:07 PM PDT 24
Peak memory 213276 kb
Host smart-7921eaf2-66ad-46c2-b11d-3fcff1139d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717626540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1717626540
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.14305477
Short name T120
Test name
Test status
Simulation time 865466985 ps
CPU time 8.49 seconds
Started Apr 30 02:58:10 PM PDT 24
Finished Apr 30 02:58:19 PM PDT 24
Peak memory 213224 kb
Host smart-f62a4a57-edc8-4fe1-9d7e-5c5ce2397f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14305477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.14305477
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1671627769
Short name T75
Test name
Test status
Simulation time 3150123076 ps
CPU time 7.01 seconds
Started Apr 30 02:58:12 PM PDT 24
Finished Apr 30 02:58:19 PM PDT 24
Peak memory 213116 kb
Host smart-83b294d6-7e21-41c6-ab3b-7cb663f8eceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671627769 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1671627769
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.214879470
Short name T239
Test name
Test status
Simulation time 46791341 ps
CPU time 1.41 seconds
Started Apr 30 02:58:10 PM PDT 24
Finished Apr 30 02:58:12 PM PDT 24
Peak memory 213076 kb
Host smart-6098b06e-f954-4615-812a-c95241e4b92d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214879470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.214879470
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.998960551
Short name T248
Test name
Test status
Simulation time 419471726 ps
CPU time 2.52 seconds
Started Apr 30 02:58:19 PM PDT 24
Finished Apr 30 02:58:22 PM PDT 24
Peak memory 204792 kb
Host smart-a11a7c5b-6e02-4347-b13c-c798fc917655
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998960551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.998960551
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.560923744
Short name T232
Test name
Test status
Simulation time 51166426 ps
CPU time 0.77 seconds
Started Apr 30 02:58:07 PM PDT 24
Finished Apr 30 02:58:08 PM PDT 24
Peak memory 204616 kb
Host smart-ffd83c06-4f5c-4bb2-a538-e64192706ccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560923744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.560923744
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3456864411
Short name T272
Test name
Test status
Simulation time 142786071 ps
CPU time 6.34 seconds
Started Apr 30 02:58:11 PM PDT 24
Finished Apr 30 02:58:18 PM PDT 24
Peak memory 204944 kb
Host smart-d733958f-5149-45a7-bb43-d2f68bdfb716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456864411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3456864411
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2409021971
Short name T119
Test name
Test status
Simulation time 514589999 ps
CPU time 3.16 seconds
Started Apr 30 02:58:13 PM PDT 24
Finished Apr 30 02:58:16 PM PDT 24
Peak memory 213148 kb
Host smart-876457fe-aee5-4264-8f91-d735848a5592
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409021971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2409021971
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4122927760
Short name T128
Test name
Test status
Simulation time 1237273870 ps
CPU time 23.75 seconds
Started Apr 30 02:58:16 PM PDT 24
Finished Apr 30 02:58:40 PM PDT 24
Peak memory 221496 kb
Host smart-a4f234fc-17d4-4a94-a759-aa7d5e587e01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122927760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4
122927760
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.305674510
Short name T41
Test name
Test status
Simulation time 68939270 ps
CPU time 2.11 seconds
Started Apr 30 02:58:15 PM PDT 24
Finished Apr 30 02:58:18 PM PDT 24
Peak memory 213100 kb
Host smart-ac87aeab-c7f7-4eee-90f9-7c87d9b6de47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305674510 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.305674510
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.38743801
Short name T81
Test name
Test status
Simulation time 286591252 ps
CPU time 2.12 seconds
Started Apr 30 02:58:11 PM PDT 24
Finished Apr 30 02:58:13 PM PDT 24
Peak memory 218620 kb
Host smart-5f672fe3-0e2c-4787-852e-5eefe352a280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.38743801
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1193665816
Short name T229
Test name
Test status
Simulation time 306340474 ps
CPU time 1.46 seconds
Started Apr 30 02:58:17 PM PDT 24
Finished Apr 30 02:58:19 PM PDT 24
Peak memory 204756 kb
Host smart-94d02cc2-0508-4fe0-b520-820f2a8827dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193665816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1193665816
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1945014562
Short name T193
Test name
Test status
Simulation time 66647269 ps
CPU time 0.88 seconds
Started Apr 30 02:58:12 PM PDT 24
Finished Apr 30 02:58:14 PM PDT 24
Peak memory 204636 kb
Host smart-e447c7bf-1f6a-439a-ac54-f7d53f9f2c9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945014562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1945014562
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3041011525
Short name T246
Test name
Test status
Simulation time 901153462 ps
CPU time 8.38 seconds
Started Apr 30 02:58:14 PM PDT 24
Finished Apr 30 02:58:23 PM PDT 24
Peak memory 204944 kb
Host smart-43bac3fe-2402-42e5-84ff-4a58392cac8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041011525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3041011525
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3554177288
Short name T114
Test name
Test status
Simulation time 459937908 ps
CPU time 2.96 seconds
Started Apr 30 02:58:13 PM PDT 24
Finished Apr 30 02:58:16 PM PDT 24
Peak memory 213228 kb
Host smart-7e415541-78bd-4910-9573-de35e65ee688
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554177288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3554177288
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.513716133
Short name T122
Test name
Test status
Simulation time 2535893790 ps
CPU time 18.86 seconds
Started Apr 30 02:58:14 PM PDT 24
Finished Apr 30 02:58:33 PM PDT 24
Peak memory 213148 kb
Host smart-b525c2cf-a677-4a63-9847-9c69674ec4c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513716133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.513716133
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3666619085
Short name T220
Test name
Test status
Simulation time 909167260 ps
CPU time 3.93 seconds
Started Apr 30 02:58:21 PM PDT 24
Finished Apr 30 02:58:26 PM PDT 24
Peak memory 217908 kb
Host smart-367aad9b-aece-488d-b500-d36ddbc99e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666619085 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3666619085
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2062161858
Short name T86
Test name
Test status
Simulation time 67547715 ps
CPU time 2.49 seconds
Started Apr 30 02:58:24 PM PDT 24
Finished Apr 30 02:58:27 PM PDT 24
Peak memory 221300 kb
Host smart-9311307f-0aba-4b8e-895c-8ec5924c6521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062161858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2062161858
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2034155005
Short name T310
Test name
Test status
Simulation time 468755196 ps
CPU time 2.52 seconds
Started Apr 30 02:58:19 PM PDT 24
Finished Apr 30 02:58:22 PM PDT 24
Peak memory 204740 kb
Host smart-5fee682f-a46d-4dda-9a7b-32cb06e715e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034155005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2034155005
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2258417949
Short name T200
Test name
Test status
Simulation time 148605351 ps
CPU time 0.71 seconds
Started Apr 30 02:58:14 PM PDT 24
Finished Apr 30 02:58:16 PM PDT 24
Peak memory 204628 kb
Host smart-827fd311-abd1-41a4-96f2-928fc076f964
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258417949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2258417949
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3909477492
Short name T109
Test name
Test status
Simulation time 918332228 ps
CPU time 7.75 seconds
Started Apr 30 02:58:23 PM PDT 24
Finished Apr 30 02:58:32 PM PDT 24
Peak memory 204936 kb
Host smart-9261ec63-2037-46a8-b2ba-3b242150c676
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909477492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3909477492
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2865172600
Short name T205
Test name
Test status
Simulation time 84964795 ps
CPU time 2.28 seconds
Started Apr 30 02:58:20 PM PDT 24
Finished Apr 30 02:58:23 PM PDT 24
Peak memory 213200 kb
Host smart-534821fb-4267-4bc2-935f-08fdf73b7bce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865172600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2865172600
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3945810340
Short name T72
Test name
Test status
Simulation time 6051937542 ps
CPU time 12.03 seconds
Started Apr 30 02:58:26 PM PDT 24
Finished Apr 30 02:58:39 PM PDT 24
Peak memory 221384 kb
Host smart-f542c015-c970-4b22-8f04-427743b7ebea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945810340 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3945810340
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1955133153
Short name T105
Test name
Test status
Simulation time 108279441 ps
CPU time 2.48 seconds
Started Apr 30 02:58:23 PM PDT 24
Finished Apr 30 02:58:26 PM PDT 24
Peak memory 213120 kb
Host smart-badb5db3-63fc-4d69-aa63-2d45b3506552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955133153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1955133153
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1895838079
Short name T201
Test name
Test status
Simulation time 1133492420 ps
CPU time 2.48 seconds
Started Apr 30 02:58:22 PM PDT 24
Finished Apr 30 02:58:25 PM PDT 24
Peak memory 204872 kb
Host smart-64181d53-e164-4280-95f7-87e64373f0f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895838079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1895838079
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1852163635
Short name T292
Test name
Test status
Simulation time 212183736 ps
CPU time 0.76 seconds
Started Apr 30 02:58:23 PM PDT 24
Finished Apr 30 02:58:24 PM PDT 24
Peak memory 204596 kb
Host smart-7ebcee99-7a0c-4570-97ad-283213fa589f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852163635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1852163635
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2532331391
Short name T257
Test name
Test status
Simulation time 824493287 ps
CPU time 7.43 seconds
Started Apr 30 02:58:27 PM PDT 24
Finished Apr 30 02:58:36 PM PDT 24
Peak memory 204892 kb
Host smart-f75061c0-5cf7-44c0-8d2c-769ae3d57be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532331391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2532331391
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1845706886
Short name T118
Test name
Test status
Simulation time 135242217 ps
CPU time 3.12 seconds
Started Apr 30 02:58:20 PM PDT 24
Finished Apr 30 02:58:24 PM PDT 24
Peak memory 213156 kb
Host smart-8c74c729-6abb-45d3-adaa-1f4b36c88d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845706886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1845706886
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1696220995
Short name T303
Test name
Test status
Simulation time 38371710 ps
CPU time 2.61 seconds
Started Apr 30 02:58:28 PM PDT 24
Finished Apr 30 02:58:32 PM PDT 24
Peak memory 220664 kb
Host smart-4d1735a1-2d6d-4351-abd7-66f9a4ed123b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696220995 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1696220995
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3100572022
Short name T305
Test name
Test status
Simulation time 285876107 ps
CPU time 2.35 seconds
Started Apr 30 02:58:25 PM PDT 24
Finished Apr 30 02:58:29 PM PDT 24
Peak memory 213120 kb
Host smart-487d37e2-b09a-4b7c-bfb7-a2f7e44f4231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100572022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3100572022
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3129015611
Short name T279
Test name
Test status
Simulation time 534269194 ps
CPU time 1.41 seconds
Started Apr 30 02:58:27 PM PDT 24
Finished Apr 30 02:58:30 PM PDT 24
Peak memory 204748 kb
Host smart-b53b1449-8b0d-4782-890c-7850481f98b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129015611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3129015611
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3639293669
Short name T192
Test name
Test status
Simulation time 49742316 ps
CPU time 0.72 seconds
Started Apr 30 02:58:26 PM PDT 24
Finished Apr 30 02:58:28 PM PDT 24
Peak memory 204524 kb
Host smart-fe705673-9ff7-4bf9-8906-482126aa9be0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639293669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3639293669
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4036580750
Short name T87
Test name
Test status
Simulation time 80294672 ps
CPU time 3.47 seconds
Started Apr 30 02:58:29 PM PDT 24
Finished Apr 30 02:58:34 PM PDT 24
Peak memory 204796 kb
Host smart-a55198f3-84a6-4ae0-b26c-504f2eafb4a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036580750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4036580750
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1056195847
Short name T294
Test name
Test status
Simulation time 94913824 ps
CPU time 3.03 seconds
Started Apr 30 02:58:29 PM PDT 24
Finished Apr 30 02:58:33 PM PDT 24
Peak memory 213112 kb
Host smart-6bacae6a-f318-4725-8946-28bb5cbba587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056195847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1056195847
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2517072280
Short name T73
Test name
Test status
Simulation time 279975261 ps
CPU time 8.51 seconds
Started Apr 30 02:58:29 PM PDT 24
Finished Apr 30 02:58:38 PM PDT 24
Peak memory 213168 kb
Host smart-a2be0110-fdcd-4f44-9428-9361ff849a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517072280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
517072280
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1201401086
Short name T269
Test name
Test status
Simulation time 439877407 ps
CPU time 2.35 seconds
Started Apr 30 02:58:34 PM PDT 24
Finished Apr 30 02:58:36 PM PDT 24
Peak memory 215760 kb
Host smart-58b04320-1b04-4b0c-82a6-e44678c718ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201401086 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1201401086
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2541124437
Short name T107
Test name
Test status
Simulation time 44413093 ps
CPU time 2.29 seconds
Started Apr 30 02:58:33 PM PDT 24
Finished Apr 30 02:58:36 PM PDT 24
Peak memory 213128 kb
Host smart-24ec1e27-77a9-47c0-bb39-d0f96b5f08ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541124437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2541124437
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1541878325
Short name T309
Test name
Test status
Simulation time 1451951504 ps
CPU time 3.59 seconds
Started Apr 30 02:58:28 PM PDT 24
Finished Apr 30 02:58:32 PM PDT 24
Peak memory 204884 kb
Host smart-6fff86e8-a5c4-4fdb-a69a-e553a35e43c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541878325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1541878325
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2754658704
Short name T230
Test name
Test status
Simulation time 49620392 ps
CPU time 0.82 seconds
Started Apr 30 02:58:27 PM PDT 24
Finished Apr 30 02:58:29 PM PDT 24
Peak memory 204612 kb
Host smart-400db652-c56b-4a4e-96cb-ae4b2f3d1c0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754658704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2754658704
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.566391925
Short name T302
Test name
Test status
Simulation time 147958934 ps
CPU time 3.8 seconds
Started Apr 30 02:58:36 PM PDT 24
Finished Apr 30 02:58:40 PM PDT 24
Peak memory 204988 kb
Host smart-3b282834-9785-4af9-a4dc-ae3d8c5ad4ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566391925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.566391925
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1233908982
Short name T203
Test name
Test status
Simulation time 82859059 ps
CPU time 4.15 seconds
Started Apr 30 02:58:32 PM PDT 24
Finished Apr 30 02:58:37 PM PDT 24
Peak memory 213256 kb
Host smart-6fa20ff7-4c8c-4056-948d-4ccc4ab9a372
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233908982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1233908982
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1177523250
Short name T241
Test name
Test status
Simulation time 3792096680 ps
CPU time 7.74 seconds
Started Apr 30 02:58:31 PM PDT 24
Finished Apr 30 02:58:39 PM PDT 24
Peak memory 216784 kb
Host smart-fbfee67b-f8d7-46c2-b4f3-f30b1f127647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177523250 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1177523250
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2800008980
Short name T108
Test name
Test status
Simulation time 106221336 ps
CPU time 2.38 seconds
Started Apr 30 02:58:39 PM PDT 24
Finished Apr 30 02:58:42 PM PDT 24
Peak memory 213036 kb
Host smart-d7d21849-cd98-4ddd-93e4-a10dbf5e4685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800008980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2800008980
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2366420483
Short name T176
Test name
Test status
Simulation time 958696582 ps
CPU time 1.75 seconds
Started Apr 30 02:58:36 PM PDT 24
Finished Apr 30 02:58:38 PM PDT 24
Peak memory 204756 kb
Host smart-a35fcd37-f441-4e17-89e1-924da9049bd8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366420483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2366420483
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2078525523
Short name T266
Test name
Test status
Simulation time 91604485 ps
CPU time 0.75 seconds
Started Apr 30 02:58:31 PM PDT 24
Finished Apr 30 02:58:33 PM PDT 24
Peak memory 204572 kb
Host smart-3d48a8c5-8bd5-4a17-8949-7d3eefdc340a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078525523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2078525523
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3023419775
Short name T85
Test name
Test status
Simulation time 1485749179 ps
CPU time 4.3 seconds
Started Apr 30 02:58:37 PM PDT 24
Finished Apr 30 02:58:42 PM PDT 24
Peak memory 205016 kb
Host smart-e39842b2-437b-4f3f-8d6a-09e4d29595d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023419775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3023419775
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.413715667
Short name T291
Test name
Test status
Simulation time 10366829971 ps
CPU time 19.49 seconds
Started Apr 30 02:58:33 PM PDT 24
Finished Apr 30 02:58:53 PM PDT 24
Peak memory 219028 kb
Host smart-70602e9e-e9f5-40ff-b698-92973d7463cb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413715667 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.413715667
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1692182042
Short name T256
Test name
Test status
Simulation time 965028217 ps
CPU time 5.11 seconds
Started Apr 30 02:58:37 PM PDT 24
Finished Apr 30 02:58:42 PM PDT 24
Peak memory 213236 kb
Host smart-70ec5906-8666-4361-87ec-518ea75546b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692182042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1692182042
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.718536889
Short name T115
Test name
Test status
Simulation time 4017885246 ps
CPU time 10.54 seconds
Started Apr 30 02:58:36 PM PDT 24
Finished Apr 30 02:58:47 PM PDT 24
Peak memory 213172 kb
Host smart-fc7ee2d6-0677-4a78-8c78-e46ad89eb4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718536889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.718536889
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2262005564
Short name T184
Test name
Test status
Simulation time 1073769251 ps
CPU time 6.01 seconds
Started Apr 30 02:58:40 PM PDT 24
Finished Apr 30 02:58:46 PM PDT 24
Peak memory 219300 kb
Host smart-a35d6f42-3bc1-405b-a4a0-ba4f3b94f6f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262005564 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2262005564
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2697700368
Short name T301
Test name
Test status
Simulation time 114017899 ps
CPU time 2.4 seconds
Started Apr 30 02:58:42 PM PDT 24
Finished Apr 30 02:58:44 PM PDT 24
Peak memory 213104 kb
Host smart-5a1f239a-6c72-456f-95c1-b2c6ed6538e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697700368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2697700368
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1311992477
Short name T247
Test name
Test status
Simulation time 1782397780 ps
CPU time 2.85 seconds
Started Apr 30 02:58:41 PM PDT 24
Finished Apr 30 02:58:44 PM PDT 24
Peak memory 204740 kb
Host smart-a7cb330b-c08e-4f57-b0e9-3a241dd50522
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311992477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1311992477
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.312079056
Short name T243
Test name
Test status
Simulation time 107078269 ps
CPU time 0.68 seconds
Started Apr 30 02:58:34 PM PDT 24
Finished Apr 30 02:58:35 PM PDT 24
Peak memory 204588 kb
Host smart-822a6a1d-7b45-4349-a5e5-36e9649ebbef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312079056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.312079056
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2906125480
Short name T95
Test name
Test status
Simulation time 83032904 ps
CPU time 3.69 seconds
Started Apr 30 02:58:38 PM PDT 24
Finished Apr 30 02:58:43 PM PDT 24
Peak memory 204868 kb
Host smart-822ac987-7e8a-44cf-aa88-4a18c8270c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906125480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2906125480
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.585950086
Short name T195
Test name
Test status
Simulation time 33958388494 ps
CPU time 25.03 seconds
Started Apr 30 02:58:41 PM PDT 24
Finished Apr 30 02:59:06 PM PDT 24
Peak memory 229584 kb
Host smart-bc4a4c27-b1ef-4fd7-abfa-d7742173be32
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585950086 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.585950086
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.617120149
Short name T223
Test name
Test status
Simulation time 276051829 ps
CPU time 6.36 seconds
Started Apr 30 02:58:39 PM PDT 24
Finished Apr 30 02:58:46 PM PDT 24
Peak memory 213112 kb
Host smart-6af85e0f-ecb7-4105-bfa2-f06a4b078fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617120149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.617120149
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2712372475
Short name T235
Test name
Test status
Simulation time 2945742836 ps
CPU time 18.41 seconds
Started Apr 30 02:58:40 PM PDT 24
Finished Apr 30 02:58:59 PM PDT 24
Peak memory 221360 kb
Host smart-f124005e-f0ea-4763-b164-39676f7cd658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712372475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
712372475
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3394126116
Short name T255
Test name
Test status
Simulation time 3929601345 ps
CPU time 7.68 seconds
Started Apr 30 02:58:42 PM PDT 24
Finished Apr 30 02:58:50 PM PDT 24
Peak memory 218140 kb
Host smart-589c62c9-4b33-4280-95cb-5726d31a5596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394126116 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3394126116
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.573093058
Short name T298
Test name
Test status
Simulation time 51061212 ps
CPU time 1.57 seconds
Started Apr 30 02:58:41 PM PDT 24
Finished Apr 30 02:58:43 PM PDT 24
Peak memory 213060 kb
Host smart-0210fea5-857b-407f-9bb9-9c4d28846ec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573093058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.573093058
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2032187709
Short name T187
Test name
Test status
Simulation time 514853819 ps
CPU time 1.78 seconds
Started Apr 30 02:58:49 PM PDT 24
Finished Apr 30 02:58:51 PM PDT 24
Peak memory 204740 kb
Host smart-d9f1226b-fdfc-48c4-becd-95bc469916ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032187709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2032187709
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3764455947
Short name T264
Test name
Test status
Simulation time 67522433 ps
CPU time 0.8 seconds
Started Apr 30 02:58:43 PM PDT 24
Finished Apr 30 02:58:45 PM PDT 24
Peak memory 204660 kb
Host smart-4fde33ea-dd79-4358-95cc-d5d97055ed0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764455947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3764455947
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1941457809
Short name T283
Test name
Test status
Simulation time 76774550 ps
CPU time 3.63 seconds
Started Apr 30 02:58:42 PM PDT 24
Finished Apr 30 02:58:47 PM PDT 24
Peak memory 204928 kb
Host smart-9a6e7518-2b4d-4900-8809-655df7d8cf4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941457809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1941457809
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.108476676
Short name T202
Test name
Test status
Simulation time 2559352349 ps
CPU time 5.04 seconds
Started Apr 30 02:58:42 PM PDT 24
Finished Apr 30 02:58:48 PM PDT 24
Peak memory 215580 kb
Host smart-bef02b4c-a97c-474d-bc37-acdf63bf3511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108476676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.108476676
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2599591200
Short name T252
Test name
Test status
Simulation time 807008471 ps
CPU time 28.2 seconds
Started Apr 30 02:57:20 PM PDT 24
Finished Apr 30 02:57:49 PM PDT 24
Peak memory 214140 kb
Host smart-6877160d-cdce-4c18-ad98-9e77261f9183
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599591200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2599591200
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2915535749
Short name T299
Test name
Test status
Simulation time 2581424025 ps
CPU time 34.96 seconds
Started Apr 30 02:57:29 PM PDT 24
Finished Apr 30 02:58:05 PM PDT 24
Peak memory 205024 kb
Host smart-ce8ba1f5-b484-430b-bd76-eba37f39e072
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915535749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2915535749
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3782278860
Short name T281
Test name
Test status
Simulation time 61456435 ps
CPU time 1.62 seconds
Started Apr 30 02:57:24 PM PDT 24
Finished Apr 30 02:57:27 PM PDT 24
Peak memory 213072 kb
Host smart-267caa5e-7daa-464e-adf8-ac796ff4d990
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782278860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3782278860
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3198512612
Short name T76
Test name
Test status
Simulation time 476647368 ps
CPU time 4.27 seconds
Started Apr 30 02:57:32 PM PDT 24
Finished Apr 30 02:57:37 PM PDT 24
Peak memory 218000 kb
Host smart-90835161-a88c-4e86-9f67-aae05bb6131c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198512612 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3198512612
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1256803210
Short name T237
Test name
Test status
Simulation time 46140957 ps
CPU time 1.53 seconds
Started Apr 30 02:57:33 PM PDT 24
Finished Apr 30 02:57:35 PM PDT 24
Peak memory 218516 kb
Host smart-d76ab78b-5472-459e-99c8-e5511fc778a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256803210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1256803210
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.762087541
Short name T190
Test name
Test status
Simulation time 10020872383 ps
CPU time 14.5 seconds
Started Apr 30 02:57:24 PM PDT 24
Finished Apr 30 02:57:39 PM PDT 24
Peak memory 204928 kb
Host smart-7d6214b6-5f5f-4650-adb1-5da3d68e8830
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762087541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.762087541
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2257270662
Short name T307
Test name
Test status
Simulation time 18009126659 ps
CPU time 40.26 seconds
Started Apr 30 02:57:22 PM PDT 24
Finished Apr 30 02:58:03 PM PDT 24
Peak memory 204952 kb
Host smart-881f7cd4-e2b9-4ed8-b743-7e57b01106be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257270662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2257270662
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4022522695
Short name T263
Test name
Test status
Simulation time 929413847 ps
CPU time 3.64 seconds
Started Apr 30 02:57:25 PM PDT 24
Finished Apr 30 02:57:29 PM PDT 24
Peak memory 204912 kb
Host smart-9519628f-63b4-4d28-9193-79fa61da40f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022522695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4022522695
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1166937955
Short name T197
Test name
Test status
Simulation time 741761869 ps
CPU time 1.71 seconds
Started Apr 30 02:57:22 PM PDT 24
Finished Apr 30 02:57:24 PM PDT 24
Peak memory 204744 kb
Host smart-938a3056-dc2b-4a20-a613-d3a64f1d2175
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166937955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
166937955
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.613959955
Short name T204
Test name
Test status
Simulation time 36308100 ps
CPU time 0.78 seconds
Started Apr 30 02:57:23 PM PDT 24
Finished Apr 30 02:57:24 PM PDT 24
Peak memory 204560 kb
Host smart-feb55707-a770-4fa1-bef6-7f4cc6c56137
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613959955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.613959955
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1944908021
Short name T245
Test name
Test status
Simulation time 792556300 ps
CPU time 3.56 seconds
Started Apr 30 02:57:16 PM PDT 24
Finished Apr 30 02:57:21 PM PDT 24
Peak memory 204792 kb
Host smart-9ced40c4-c997-477e-84e7-59c5a710e8c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944908021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1944908021
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1855566993
Short name T206
Test name
Test status
Simulation time 165278927 ps
CPU time 1.09 seconds
Started Apr 30 02:57:17 PM PDT 24
Finished Apr 30 02:57:19 PM PDT 24
Peak memory 204648 kb
Host smart-04873d09-854e-477d-8862-6846d8d8433a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855566993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1855566993
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3989762247
Short name T59
Test name
Test status
Simulation time 117176923 ps
CPU time 0.82 seconds
Started Apr 30 02:57:14 PM PDT 24
Finished Apr 30 02:57:15 PM PDT 24
Peak memory 204540 kb
Host smart-30441d28-af32-4d4e-9e2c-41eb14bc6ee4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989762247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
989762247
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2118283587
Short name T293
Test name
Test status
Simulation time 41079444 ps
CPU time 0.7 seconds
Started Apr 30 02:57:25 PM PDT 24
Finished Apr 30 02:57:27 PM PDT 24
Peak memory 204592 kb
Host smart-11a3386b-233e-4317-b2cc-06ab3a7c9b41
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118283587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2118283587
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4079970101
Short name T180
Test name
Test status
Simulation time 42663665 ps
CPU time 0.74 seconds
Started Apr 30 02:57:24 PM PDT 24
Finished Apr 30 02:57:26 PM PDT 24
Peak memory 204636 kb
Host smart-ae03e531-70b0-4838-a1d5-d09f1f954a78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079970101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4079970101
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3281006173
Short name T231
Test name
Test status
Simulation time 562720135 ps
CPU time 8.05 seconds
Started Apr 30 02:57:33 PM PDT 24
Finished Apr 30 02:57:42 PM PDT 24
Peak memory 204972 kb
Host smart-3459fe0a-eee7-4d6f-84eb-a96aeb0827ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281006173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3281006173
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3762796362
Short name T262
Test name
Test status
Simulation time 892506938 ps
CPU time 5.69 seconds
Started Apr 30 02:57:22 PM PDT 24
Finished Apr 30 02:57:29 PM PDT 24
Peak memory 213244 kb
Host smart-054756cd-bcd7-4fd6-9ee9-e6875243d79c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762796362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3762796362
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2126938993
Short name T296
Test name
Test status
Simulation time 1145737667 ps
CPU time 29.83 seconds
Started Apr 30 02:57:31 PM PDT 24
Finished Apr 30 02:58:01 PM PDT 24
Peak memory 204908 kb
Host smart-eba5efbd-0342-45ca-9f23-8c0ce1c6c6dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126938993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2126938993
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1204990596
Short name T104
Test name
Test status
Simulation time 2576970082 ps
CPU time 32.93 seconds
Started Apr 30 02:57:37 PM PDT 24
Finished Apr 30 02:58:10 PM PDT 24
Peak memory 205008 kb
Host smart-1e10ac68-e55e-4fa2-a2ef-88cb8b8a3ee8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204990596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1204990596
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3217590916
Short name T84
Test name
Test status
Simulation time 172115739 ps
CPU time 2.23 seconds
Started Apr 30 02:57:31 PM PDT 24
Finished Apr 30 02:57:34 PM PDT 24
Peak memory 213088 kb
Host smart-cf24a779-20eb-4b1c-a07b-a04a6e522116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217590916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3217590916
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1679652804
Short name T254
Test name
Test status
Simulation time 81790977 ps
CPU time 2.44 seconds
Started Apr 30 02:57:39 PM PDT 24
Finished Apr 30 02:57:42 PM PDT 24
Peak memory 213184 kb
Host smart-276c6020-84a8-44b7-804f-953e13d8c641
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679652804 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1679652804
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1023333985
Short name T251
Test name
Test status
Simulation time 55402553 ps
CPU time 2.14 seconds
Started Apr 30 02:57:30 PM PDT 24
Finished Apr 30 02:57:33 PM PDT 24
Peak memory 213124 kb
Host smart-ef609c51-bbda-4a10-a825-031cf848edfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023333985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1023333985
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2651097984
Short name T178
Test name
Test status
Simulation time 5042114220 ps
CPU time 20.64 seconds
Started Apr 30 02:57:34 PM PDT 24
Finished Apr 30 02:57:55 PM PDT 24
Peak memory 204944 kb
Host smart-520e2406-1641-488d-82ab-82eab0c988c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651097984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2651097984
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1194429198
Short name T275
Test name
Test status
Simulation time 14958591124 ps
CPU time 39.79 seconds
Started Apr 30 02:57:32 PM PDT 24
Finished Apr 30 02:58:13 PM PDT 24
Peak memory 204912 kb
Host smart-dde7c327-bc12-440a-aec0-6541eccbceb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194429198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1194429198
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3490273189
Short name T236
Test name
Test status
Simulation time 1926684038 ps
CPU time 6.3 seconds
Started Apr 30 02:57:30 PM PDT 24
Finished Apr 30 02:57:37 PM PDT 24
Peak memory 204724 kb
Host smart-c6f9e8eb-8c15-46fa-ba24-32eaa444cd76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490273189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
490273189
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.399704188
Short name T284
Test name
Test status
Simulation time 94152437 ps
CPU time 0.78 seconds
Started Apr 30 02:57:33 PM PDT 24
Finished Apr 30 02:57:34 PM PDT 24
Peak memory 204620 kb
Host smart-056af165-0f91-4a7b-a8f9-40c7d134ac10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399704188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.399704188
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3759010429
Short name T194
Test name
Test status
Simulation time 837884520 ps
CPU time 2.44 seconds
Started Apr 30 02:57:34 PM PDT 24
Finished Apr 30 02:57:37 PM PDT 24
Peak memory 204744 kb
Host smart-e0c6f9cd-8e27-457c-ab5c-e76cc2eabe00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759010429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3759010429
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.739516736
Short name T286
Test name
Test status
Simulation time 64257227 ps
CPU time 0.9 seconds
Started Apr 30 02:57:32 PM PDT 24
Finished Apr 30 02:57:34 PM PDT 24
Peak memory 204612 kb
Host smart-ed91d36c-c912-4959-8ded-710448122f32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739516736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.739516736
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2263569192
Short name T270
Test name
Test status
Simulation time 34272785 ps
CPU time 0.75 seconds
Started Apr 30 02:57:32 PM PDT 24
Finished Apr 30 02:57:33 PM PDT 24
Peak memory 204612 kb
Host smart-8a77e35b-5bcc-416e-957e-91d8064fcd18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263569192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
263569192
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.770140484
Short name T212
Test name
Test status
Simulation time 18458241 ps
CPU time 0.72 seconds
Started Apr 30 02:57:28 PM PDT 24
Finished Apr 30 02:57:29 PM PDT 24
Peak memory 204544 kb
Host smart-d14f72eb-555b-4cff-b7b3-36c3d5eecfb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770140484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.770140484
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.58782735
Short name T253
Test name
Test status
Simulation time 26252046 ps
CPU time 0.69 seconds
Started Apr 30 02:57:32 PM PDT 24
Finished Apr 30 02:57:33 PM PDT 24
Peak memory 204540 kb
Host smart-7f257a86-1898-4e0a-a504-5d0b653940c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58782735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.58782735
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.255423822
Short name T280
Test name
Test status
Simulation time 324113875 ps
CPU time 3.84 seconds
Started Apr 30 02:57:45 PM PDT 24
Finished Apr 30 02:57:49 PM PDT 24
Peak memory 204856 kb
Host smart-5110352b-7603-41b9-8819-5ed9ddb3e1d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255423822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.255423822
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3709486174
Short name T209
Test name
Test status
Simulation time 321968737 ps
CPU time 3.2 seconds
Started Apr 30 02:57:28 PM PDT 24
Finished Apr 30 02:57:32 PM PDT 24
Peak memory 213200 kb
Host smart-1873f060-9543-45bb-aa90-8cc6fcedde47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709486174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3709486174
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.260068272
Short name T258
Test name
Test status
Simulation time 6017280712 ps
CPU time 22.3 seconds
Started Apr 30 02:58:52 PM PDT 24
Finished Apr 30 02:59:15 PM PDT 24
Peak memory 221280 kb
Host smart-09432aeb-4fbd-441f-8a22-108813d2ed74
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260068272 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.260068272
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.8471738
Short name T295
Test name
Test status
Simulation time 28997514498 ps
CPU time 28.18 seconds
Started Apr 30 02:58:49 PM PDT 24
Finished Apr 30 02:59:18 PM PDT 24
Peak memory 220896 kb
Host smart-5de759c5-5c9e-48d8-99fb-44340bc0c0dc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8471738 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.8471738
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1509016030
Short name T188
Test name
Test status
Simulation time 6944130221 ps
CPU time 13.65 seconds
Started Apr 30 02:58:50 PM PDT 24
Finished Apr 30 02:59:04 PM PDT 24
Peak memory 219620 kb
Host smart-a70cc43e-3312-4909-8ab5-1140b2d04486
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509016030 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.1509016030
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.2757073704
Short name T276
Test name
Test status
Simulation time 17525162065 ps
CPU time 50.46 seconds
Started Apr 30 02:58:49 PM PDT 24
Finished Apr 30 02:59:40 PM PDT 24
Peak memory 221168 kb
Host smart-ea54ba07-0a96-474d-83d8-f1be6e0a7afe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757073704 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.2757073704
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1842161063
Short name T99
Test name
Test status
Simulation time 2321890369 ps
CPU time 67.89 seconds
Started Apr 30 02:57:36 PM PDT 24
Finished Apr 30 02:58:44 PM PDT 24
Peak memory 217216 kb
Host smart-dee1caca-8e0e-459f-8004-a18949e3a661
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842161063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1842161063
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2665741012
Short name T214
Test name
Test status
Simulation time 10243187963 ps
CPU time 35.03 seconds
Started Apr 30 02:57:46 PM PDT 24
Finished Apr 30 02:58:21 PM PDT 24
Peak memory 205076 kb
Host smart-efd50c96-b1ec-4b17-b478-1380652394e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665741012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2665741012
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.487876367
Short name T106
Test name
Test status
Simulation time 150037763 ps
CPU time 2.55 seconds
Started Apr 30 02:57:46 PM PDT 24
Finished Apr 30 02:57:49 PM PDT 24
Peak memory 213188 kb
Host smart-8fb2cff3-c696-4122-a835-3e8e56d06b59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487876367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.487876367
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2545569012
Short name T288
Test name
Test status
Simulation time 95435303 ps
CPU time 2.32 seconds
Started Apr 30 02:57:45 PM PDT 24
Finished Apr 30 02:57:48 PM PDT 24
Peak memory 213272 kb
Host smart-1112e2f2-7067-46ca-8c48-101c11958ded
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545569012 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2545569012
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.732294473
Short name T100
Test name
Test status
Simulation time 105282802 ps
CPU time 2.38 seconds
Started Apr 30 02:57:48 PM PDT 24
Finished Apr 30 02:57:50 PM PDT 24
Peak memory 213036 kb
Host smart-8114e291-d3d4-455f-bca0-61442a6cc819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732294473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.732294473
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2154090502
Short name T198
Test name
Test status
Simulation time 13956404856 ps
CPU time 16.63 seconds
Started Apr 30 02:57:38 PM PDT 24
Finished Apr 30 02:57:56 PM PDT 24
Peak memory 204972 kb
Host smart-986e20e0-e44a-403e-ba83-35ef2ac1d6b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154090502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2154090502
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.106222132
Short name T300
Test name
Test status
Simulation time 9017354226 ps
CPU time 25.28 seconds
Started Apr 30 02:57:38 PM PDT 24
Finished Apr 30 02:58:04 PM PDT 24
Peak memory 204876 kb
Host smart-96e7b2b9-fdf5-412a-8e86-068232ef0a50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106222132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_bit_bash.106222132
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.227563944
Short name T92
Test name
Test status
Simulation time 455166954 ps
CPU time 1.44 seconds
Started Apr 30 02:57:35 PM PDT 24
Finished Apr 30 02:57:37 PM PDT 24
Peak memory 204892 kb
Host smart-a6a56222-aa4c-40ac-a432-12387c77f8fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227563944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.227563944
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1171223308
Short name T233
Test name
Test status
Simulation time 230836731 ps
CPU time 1.37 seconds
Started Apr 30 02:57:38 PM PDT 24
Finished Apr 30 02:57:40 PM PDT 24
Peak memory 204756 kb
Host smart-a832abbf-0655-46f5-9b87-6c044e3ab248
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171223308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
171223308
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2058127357
Short name T244
Test name
Test status
Simulation time 274749338 ps
CPU time 1.48 seconds
Started Apr 30 02:57:38 PM PDT 24
Finished Apr 30 02:57:40 PM PDT 24
Peak memory 204612 kb
Host smart-b9f23b67-4f06-4b0b-a891-4443fb433f06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058127357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2058127357
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.263285161
Short name T179
Test name
Test status
Simulation time 452838344 ps
CPU time 1.51 seconds
Started Apr 30 02:57:39 PM PDT 24
Finished Apr 30 02:57:41 PM PDT 24
Peak memory 204812 kb
Host smart-781c7a5a-f450-4c8a-af5f-88f54a5c2e70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263285161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.263285161
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.671140543
Short name T271
Test name
Test status
Simulation time 74694812 ps
CPU time 0.78 seconds
Started Apr 30 02:57:35 PM PDT 24
Finished Apr 30 02:57:37 PM PDT 24
Peak memory 204656 kb
Host smart-ebdf3da1-c3c0-459b-8acd-61a748075272
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671140543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.671140543
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3701500247
Short name T285
Test name
Test status
Simulation time 54041352 ps
CPU time 0.72 seconds
Started Apr 30 02:57:38 PM PDT 24
Finished Apr 30 02:57:39 PM PDT 24
Peak memory 204832 kb
Host smart-798dc1e3-94bf-45a5-b132-51071df822e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701500247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
701500247
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1732283639
Short name T177
Test name
Test status
Simulation time 18638340 ps
CPU time 0.7 seconds
Started Apr 30 02:57:46 PM PDT 24
Finished Apr 30 02:57:47 PM PDT 24
Peak memory 204540 kb
Host smart-c49c57a1-5321-4700-b778-27d24ac77266
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732283639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1732283639
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.55937359
Short name T306
Test name
Test status
Simulation time 51601133 ps
CPU time 0.69 seconds
Started Apr 30 02:57:49 PM PDT 24
Finished Apr 30 02:57:50 PM PDT 24
Peak memory 204564 kb
Host smart-92388925-41d9-4978-aa81-1ef492dec716
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55937359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.55937359
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.482776091
Short name T110
Test name
Test status
Simulation time 956100727 ps
CPU time 7.35 seconds
Started Apr 30 02:57:46 PM PDT 24
Finished Apr 30 02:57:53 PM PDT 24
Peak memory 204964 kb
Host smart-c8c86d1b-2210-41be-a086-fc8c72c631ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482776091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.482776091
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4064446585
Short name T250
Test name
Test status
Simulation time 569384476 ps
CPU time 4.07 seconds
Started Apr 30 02:57:37 PM PDT 24
Finished Apr 30 02:57:42 PM PDT 24
Peak memory 213124 kb
Host smart-e35f3d58-2fb5-4f74-b05f-c464f0839786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064446585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4064446585
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3692475579
Short name T304
Test name
Test status
Simulation time 2197270372 ps
CPU time 21.93 seconds
Started Apr 30 02:57:46 PM PDT 24
Finished Apr 30 02:58:08 PM PDT 24
Peak memory 213148 kb
Host smart-133fd04f-9110-4ad5-92d3-aa717d1c17a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692475579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3692475579
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.769905151
Short name T196
Test name
Test status
Simulation time 3643126348 ps
CPU time 5.72 seconds
Started Apr 30 02:57:53 PM PDT 24
Finished Apr 30 02:57:59 PM PDT 24
Peak memory 221516 kb
Host smart-05be71a8-c6a1-418b-8d2b-44ab1549239a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769905151 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.769905151
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1127508051
Short name T208
Test name
Test status
Simulation time 200273264 ps
CPU time 1.59 seconds
Started Apr 30 02:57:54 PM PDT 24
Finished Apr 30 02:57:56 PM PDT 24
Peak memory 213056 kb
Host smart-91a625d8-83b1-412b-ae2b-f91d53bc8780
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127508051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1127508051
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1927012275
Short name T222
Test name
Test status
Simulation time 295716347 ps
CPU time 1.32 seconds
Started Apr 30 02:57:49 PM PDT 24
Finished Apr 30 02:57:51 PM PDT 24
Peak memory 204796 kb
Host smart-1742601c-334a-491a-9891-bb3b33cbe88d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927012275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
927012275
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3754016651
Short name T189
Test name
Test status
Simulation time 33402644 ps
CPU time 0.77 seconds
Started Apr 30 02:57:46 PM PDT 24
Finished Apr 30 02:57:47 PM PDT 24
Peak memory 204580 kb
Host smart-9fbd2baa-2c4d-4a76-a882-9ddf57ea3afa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754016651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
754016651
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3732274942
Short name T238
Test name
Test status
Simulation time 147008979 ps
CPU time 6.73 seconds
Started Apr 30 02:57:52 PM PDT 24
Finished Apr 30 02:58:00 PM PDT 24
Peak memory 204864 kb
Host smart-02c9ba73-934d-43a1-a5f8-6e8e11d1a88b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732274942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3732274942
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.121745531
Short name T265
Test name
Test status
Simulation time 233998129 ps
CPU time 6.8 seconds
Started Apr 30 02:57:49 PM PDT 24
Finished Apr 30 02:57:56 PM PDT 24
Peak memory 213448 kb
Host smart-ca97c2f0-9653-464f-a3bf-40a08215c928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121745531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.121745531
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1754035071
Short name T113
Test name
Test status
Simulation time 262917897 ps
CPU time 2.15 seconds
Started Apr 30 02:57:52 PM PDT 24
Finished Apr 30 02:57:54 PM PDT 24
Peak memory 214904 kb
Host smart-b5f01221-3b2c-446c-9f7a-f02dc95b2909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754035071 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1754035071
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.592428931
Short name T103
Test name
Test status
Simulation time 102997407 ps
CPU time 1.59 seconds
Started Apr 30 02:57:58 PM PDT 24
Finished Apr 30 02:58:00 PM PDT 24
Peak memory 218036 kb
Host smart-8ab65f7d-cd26-4be8-ba0e-8292a3109968
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592428931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.592428931
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1044072230
Short name T228
Test name
Test status
Simulation time 457089475 ps
CPU time 1.42 seconds
Started Apr 30 02:57:58 PM PDT 24
Finished Apr 30 02:58:00 PM PDT 24
Peak memory 204724 kb
Host smart-57b44613-fb7e-4235-98bc-6d0eead812f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044072230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
044072230
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2001934987
Short name T211
Test name
Test status
Simulation time 138645332 ps
CPU time 0.81 seconds
Started Apr 30 02:57:51 PM PDT 24
Finished Apr 30 02:57:52 PM PDT 24
Peak memory 204556 kb
Host smart-b3a28a73-0be2-423f-8f96-67946c387382
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001934987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
001934987
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3244906162
Short name T65
Test name
Test status
Simulation time 225398315 ps
CPU time 2.41 seconds
Started Apr 30 02:57:58 PM PDT 24
Finished Apr 30 02:58:01 PM PDT 24
Peak memory 221288 kb
Host smart-04d0a550-c7d9-4547-b296-992a8e483657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244906162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3244906162
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2274994865
Short name T61
Test name
Test status
Simulation time 593203043 ps
CPU time 8.49 seconds
Started Apr 30 02:57:52 PM PDT 24
Finished Apr 30 02:58:01 PM PDT 24
Peak memory 213212 kb
Host smart-43fa2ad7-314a-42c2-8c82-2c34cdc0f352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274994865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2274994865
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1836055462
Short name T216
Test name
Test status
Simulation time 157724031 ps
CPU time 2.65 seconds
Started Apr 30 02:58:01 PM PDT 24
Finished Apr 30 02:58:04 PM PDT 24
Peak memory 218200 kb
Host smart-523b82e4-ca4b-4f33-8890-ffd4637b1180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836055462 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1836055462
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4187704352
Short name T80
Test name
Test status
Simulation time 164581573 ps
CPU time 2.35 seconds
Started Apr 30 02:57:51 PM PDT 24
Finished Apr 30 02:57:54 PM PDT 24
Peak memory 213220 kb
Host smart-9ba37030-485b-4a97-8e9d-e13cb510bfd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187704352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4187704352
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3933293785
Short name T199
Test name
Test status
Simulation time 1026355512 ps
CPU time 4.07 seconds
Started Apr 30 02:57:52 PM PDT 24
Finished Apr 30 02:57:57 PM PDT 24
Peak memory 204876 kb
Host smart-f51f1dbf-9715-435e-ad4d-42c3b1d74d10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933293785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
933293785
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3383227927
Short name T60
Test name
Test status
Simulation time 68693915 ps
CPU time 0.73 seconds
Started Apr 30 02:57:53 PM PDT 24
Finished Apr 30 02:57:54 PM PDT 24
Peak memory 204612 kb
Host smart-8fe845e2-8fed-46f7-b7b9-c96188834ba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383227927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
383227927
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3245164410
Short name T43
Test name
Test status
Simulation time 157343437 ps
CPU time 6.33 seconds
Started Apr 30 02:57:59 PM PDT 24
Finished Apr 30 02:58:06 PM PDT 24
Peak memory 204920 kb
Host smart-83067a80-c1b7-44c6-9059-59dbb6d37821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245164410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3245164410
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2510887887
Short name T249
Test name
Test status
Simulation time 5646467402 ps
CPU time 22.24 seconds
Started Apr 30 02:57:54 PM PDT 24
Finished Apr 30 02:58:17 PM PDT 24
Peak memory 219408 kb
Host smart-19b96531-8610-4acd-8b5d-8347e91fa601
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510887887 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2510887887
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2349024610
Short name T217
Test name
Test status
Simulation time 697609022 ps
CPU time 4.29 seconds
Started Apr 30 02:57:54 PM PDT 24
Finished Apr 30 02:57:59 PM PDT 24
Peak memory 213208 kb
Host smart-35b3a3d3-1891-4ae9-857f-44384ac62d00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349024610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2349024610
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3488566000
Short name T121
Test name
Test status
Simulation time 2319801160 ps
CPU time 11.35 seconds
Started Apr 30 02:57:51 PM PDT 24
Finished Apr 30 02:58:02 PM PDT 24
Peak memory 215708 kb
Host smart-16d4f1b3-9d12-4b48-b761-f1ba62a38397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488566000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3488566000
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.48765869
Short name T210
Test name
Test status
Simulation time 42662368 ps
CPU time 2.86 seconds
Started Apr 30 02:57:59 PM PDT 24
Finished Apr 30 02:58:03 PM PDT 24
Peak memory 221140 kb
Host smart-ab940122-88b8-4f2c-b8dd-7012b65633e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48765869 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.48765869
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2596216081
Short name T94
Test name
Test status
Simulation time 214640383 ps
CPU time 2.38 seconds
Started Apr 30 02:58:01 PM PDT 24
Finished Apr 30 02:58:04 PM PDT 24
Peak memory 213172 kb
Host smart-35bdfd25-e17c-488c-bd66-44e0ccc6accb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596216081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2596216081
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.763978758
Short name T261
Test name
Test status
Simulation time 1376183295 ps
CPU time 2.31 seconds
Started Apr 30 02:58:04 PM PDT 24
Finished Apr 30 02:58:07 PM PDT 24
Peak memory 204800 kb
Host smart-d2a737c6-17f6-4f79-9225-dacdb850055a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763978758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.763978758
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.315378249
Short name T57
Test name
Test status
Simulation time 225897060 ps
CPU time 0.73 seconds
Started Apr 30 02:57:59 PM PDT 24
Finished Apr 30 02:58:00 PM PDT 24
Peak memory 204564 kb
Host smart-95ed6c95-a694-4e24-a5ca-faba5988b0bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315378249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.315378249
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.795911446
Short name T97
Test name
Test status
Simulation time 548046915 ps
CPU time 7.87 seconds
Started Apr 30 02:58:00 PM PDT 24
Finished Apr 30 02:58:08 PM PDT 24
Peak memory 204992 kb
Host smart-0e497d37-44ed-4602-a9b4-4c270b001594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795911446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.795911446
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1753178246
Short name T74
Test name
Test status
Simulation time 167496556 ps
CPU time 3.58 seconds
Started Apr 30 02:57:59 PM PDT 24
Finished Apr 30 02:58:03 PM PDT 24
Peak memory 213208 kb
Host smart-e270ae52-b9e6-4822-af32-95a7f9dcae7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753178246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1753178246
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.468321112
Short name T124
Test name
Test status
Simulation time 341643762 ps
CPU time 8.45 seconds
Started Apr 30 02:58:01 PM PDT 24
Finished Apr 30 02:58:10 PM PDT 24
Peak memory 221280 kb
Host smart-72de052d-bee1-464b-913b-5fb491d9b95f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468321112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.468321112
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4000994235
Short name T273
Test name
Test status
Simulation time 144243055 ps
CPU time 2.16 seconds
Started Apr 30 02:58:17 PM PDT 24
Finished Apr 30 02:58:20 PM PDT 24
Peak memory 216148 kb
Host smart-27b35d57-1aa2-42b0-88a3-a586de0fb8b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000994235 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4000994235
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1677828665
Short name T242
Test name
Test status
Simulation time 598929468 ps
CPU time 2.07 seconds
Started Apr 30 02:58:08 PM PDT 24
Finished Apr 30 02:58:11 PM PDT 24
Peak memory 213124 kb
Host smart-0cca4ebd-98a6-48a4-adbf-3de297bb0745
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677828665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1677828665
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3330188441
Short name T227
Test name
Test status
Simulation time 1132192891 ps
CPU time 2.74 seconds
Started Apr 30 02:57:58 PM PDT 24
Finished Apr 30 02:58:01 PM PDT 24
Peak memory 204804 kb
Host smart-979bfaf6-0bea-485d-930e-fdac3a5555ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330188441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
330188441
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4036810514
Short name T185
Test name
Test status
Simulation time 56032562 ps
CPU time 0.78 seconds
Started Apr 30 02:58:06 PM PDT 24
Finished Apr 30 02:58:07 PM PDT 24
Peak memory 204620 kb
Host smart-e0061aa8-edff-4814-adec-db0314fe6063
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036810514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
036810514
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4020023074
Short name T111
Test name
Test status
Simulation time 3524729419 ps
CPU time 8.25 seconds
Started Apr 30 02:58:08 PM PDT 24
Finished Apr 30 02:58:17 PM PDT 24
Peak memory 205028 kb
Host smart-55e7c84d-e9b2-4bf0-8a0d-1dce97793da6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020023074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.4020023074
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3615354599
Short name T64
Test name
Test status
Simulation time 16591974812 ps
CPU time 20.39 seconds
Started Apr 30 02:58:04 PM PDT 24
Finished Apr 30 02:58:25 PM PDT 24
Peak memory 214528 kb
Host smart-1c150e96-6e28-4ff8-94a7-12099baffd7c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615354599 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3615354599
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2438292793
Short name T67
Test name
Test status
Simulation time 162414831 ps
CPU time 2.91 seconds
Started Apr 30 02:58:04 PM PDT 24
Finished Apr 30 02:58:08 PM PDT 24
Peak memory 213136 kb
Host smart-54e21fe2-5302-4559-b33d-9baa3f291ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438292793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2438292793
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3720783203
Short name T308
Test name
Test status
Simulation time 901684597 ps
CPU time 17.9 seconds
Started Apr 30 02:58:06 PM PDT 24
Finished Apr 30 02:58:25 PM PDT 24
Peak memory 213200 kb
Host smart-de913c9a-b3ab-46cf-bf23-2e7a8a557ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720783203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3720783203
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2748626946
Short name T143
Test name
Test status
Simulation time 27827068 ps
CPU time 0.71 seconds
Started Apr 30 02:40:51 PM PDT 24
Finished Apr 30 02:40:52 PM PDT 24
Peak memory 205008 kb
Host smart-1e7124fa-0349-4b62-b45c-ba6b65c02f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748626946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2748626946
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3848396936
Short name T20
Test name
Test status
Simulation time 2735980592 ps
CPU time 3.92 seconds
Started Apr 30 02:40:45 PM PDT 24
Finished Apr 30 02:40:50 PM PDT 24
Peak memory 205488 kb
Host smart-2a7120ce-2477-42e9-9793-df2053bd798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848396936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3848396936
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1958999128
Short name T9
Test name
Test status
Simulation time 1671772962 ps
CPU time 5.84 seconds
Started Apr 30 02:40:44 PM PDT 24
Finished Apr 30 02:40:50 PM PDT 24
Peak memory 205380 kb
Host smart-f7d3fe55-a37d-4a33-86bf-6c901c33127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958999128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1958999128
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.292725934
Short name T18
Test name
Test status
Simulation time 68864842 ps
CPU time 0.76 seconds
Started Apr 30 02:40:50 PM PDT 24
Finished Apr 30 02:40:51 PM PDT 24
Peak memory 205056 kb
Host smart-2bd19b84-97f1-466b-ba9d-d79f569a78c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292725934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.292725934
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3918727923
Short name T164
Test name
Test status
Simulation time 60615316 ps
CPU time 0.82 seconds
Started Apr 30 02:40:52 PM PDT 24
Finished Apr 30 02:40:54 PM PDT 24
Peak memory 204988 kb
Host smart-048349ad-042b-4865-9db0-db2f06d148ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918727923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3918727923
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1273018327
Short name T36
Test name
Test status
Simulation time 233026247 ps
CPU time 1.51 seconds
Started Apr 30 02:40:49 PM PDT 24
Finished Apr 30 02:40:51 PM PDT 24
Peak memory 205184 kb
Host smart-2d949abd-bf2a-4f77-ae8e-681c1fdcab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273018327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1273018327
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1159006043
Short name T173
Test name
Test status
Simulation time 200350692 ps
CPU time 0.81 seconds
Started Apr 30 02:40:52 PM PDT 24
Finished Apr 30 02:40:53 PM PDT 24
Peak memory 205000 kb
Host smart-5bdbb3d0-7c8a-4ae2-a825-048ae0624b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159006043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1159006043
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.918507567
Short name T53
Test name
Test status
Simulation time 108216505 ps
CPU time 1.09 seconds
Started Apr 30 02:40:53 PM PDT 24
Finished Apr 30 02:40:55 PM PDT 24
Peak memory 205036 kb
Host smart-31693f2f-c913-4042-ac75-710c00178a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918507567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.918507567
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4083529666
Short name T132
Test name
Test status
Simulation time 75485827 ps
CPU time 0.76 seconds
Started Apr 30 02:40:48 PM PDT 24
Finished Apr 30 02:40:49 PM PDT 24
Peak memory 205180 kb
Host smart-a207798b-b0ca-4e42-9d2c-a4f1e21b7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083529666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4083529666
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2492028482
Short name T69
Test name
Test status
Simulation time 318597781 ps
CPU time 1.85 seconds
Started Apr 30 02:40:50 PM PDT 24
Finished Apr 30 02:40:52 PM PDT 24
Peak memory 205372 kb
Host smart-0fcf276d-a2a7-4868-a39e-0431b9ec1293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492028482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2492028482
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.360000176
Short name T78
Test name
Test status
Simulation time 148561563 ps
CPU time 0.91 seconds
Started Apr 30 02:40:50 PM PDT 24
Finished Apr 30 02:40:51 PM PDT 24
Peak memory 205172 kb
Host smart-a5be920d-429d-4857-b3fc-71ff19d984ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360000176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.360000176
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3931314863
Short name T34
Test name
Test status
Simulation time 279607588 ps
CPU time 1.24 seconds
Started Apr 30 02:40:49 PM PDT 24
Finished Apr 30 02:40:51 PM PDT 24
Peak memory 229400 kb
Host smart-a12af114-f4ae-4c6a-b996-39a74bb27be7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931314863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3931314863
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2227368438
Short name T169
Test name
Test status
Simulation time 982245850 ps
CPU time 2.39 seconds
Started Apr 30 02:40:43 PM PDT 24
Finished Apr 30 02:40:46 PM PDT 24
Peak memory 205228 kb
Host smart-e7877cdc-d7c6-49d7-86ba-792c94ec528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227368438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2227368438
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4065472100
Short name T37
Test name
Test status
Simulation time 1031436617 ps
CPU time 4.09 seconds
Started Apr 30 02:40:44 PM PDT 24
Finished Apr 30 02:40:49 PM PDT 24
Peak memory 205292 kb
Host smart-d806e00e-dadb-4efc-81c4-f1ee6f546309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065472100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4065472100
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1398725761
Short name T26
Test name
Test status
Simulation time 88936346 ps
CPU time 0.81 seconds
Started Apr 30 02:40:57 PM PDT 24
Finished Apr 30 02:40:59 PM PDT 24
Peak memory 205104 kb
Host smart-0a69a685-6f90-44de-8bb6-d2321c9be924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398725761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1398725761
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.369894861
Short name T156
Test name
Test status
Simulation time 87542821 ps
CPU time 0.72 seconds
Started Apr 30 02:40:56 PM PDT 24
Finished Apr 30 02:40:57 PM PDT 24
Peak memory 205096 kb
Host smart-21d6756d-e7e4-4934-b82c-9acd766e2b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369894861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.369894861
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2036098649
Short name T21
Test name
Test status
Simulation time 3183626472 ps
CPU time 3.48 seconds
Started Apr 30 02:40:51 PM PDT 24
Finished Apr 30 02:40:55 PM PDT 24
Peak memory 205384 kb
Host smart-f71dc564-034f-4493-989a-ec325e4193fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036098649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2036098649
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3016624881
Short name T22
Test name
Test status
Simulation time 1527825701 ps
CPU time 1.55 seconds
Started Apr 30 02:40:53 PM PDT 24
Finished Apr 30 02:40:55 PM PDT 24
Peak memory 205288 kb
Host smart-f26b02b5-cc88-41ec-a84d-92045e2b03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016624881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3016624881
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3281415419
Short name T7
Test name
Test status
Simulation time 84188883 ps
CPU time 0.92 seconds
Started Apr 30 02:40:49 PM PDT 24
Finished Apr 30 02:40:51 PM PDT 24
Peak memory 205032 kb
Host smart-10a5c2d6-67d2-49dc-9364-289dabac0e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281415419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3281415419
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3552783502
Short name T4
Test name
Test status
Simulation time 2275652513 ps
CPU time 5.1 seconds
Started Apr 30 02:40:55 PM PDT 24
Finished Apr 30 02:41:01 PM PDT 24
Peak memory 205520 kb
Host smart-66085b97-a06b-49de-a1e1-ef4d2cce9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552783502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3552783502
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2481923202
Short name T130
Test name
Test status
Simulation time 40197780 ps
CPU time 0.77 seconds
Started Apr 30 02:40:55 PM PDT 24
Finished Apr 30 02:40:57 PM PDT 24
Peak memory 205132 kb
Host smart-ceeaa5a4-7a75-4d6b-b85c-b3a44033d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481923202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2481923202
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2314880138
Short name T116
Test name
Test status
Simulation time 99840502 ps
CPU time 0.84 seconds
Started Apr 30 02:40:49 PM PDT 24
Finished Apr 30 02:40:50 PM PDT 24
Peak memory 205040 kb
Host smart-e4adfe82-1e3f-4fbd-8ed9-d7cb47c364cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314880138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2314880138
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.552239149
Short name T31
Test name
Test status
Simulation time 702952088 ps
CPU time 0.94 seconds
Started Apr 30 02:41:03 PM PDT 24
Finished Apr 30 02:41:04 PM PDT 24
Peak memory 204860 kb
Host smart-00c43404-b92f-4dcf-bf36-694f94e44afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552239149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.552239149
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.960977205
Short name T2
Test name
Test status
Simulation time 262319652 ps
CPU time 0.98 seconds
Started Apr 30 02:40:57 PM PDT 24
Finished Apr 30 02:40:58 PM PDT 24
Peak memory 205280 kb
Host smart-0e70346e-1f3e-4a27-8450-1e0f19deab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960977205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.960977205
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1376768093
Short name T163
Test name
Test status
Simulation time 32944107 ps
CPU time 0.75 seconds
Started Apr 30 02:40:48 PM PDT 24
Finished Apr 30 02:40:49 PM PDT 24
Peak memory 205184 kb
Host smart-7e314526-6eca-4a30-a34d-dfda342a5544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376768093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1376768093
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2526254935
Short name T129
Test name
Test status
Simulation time 283557114 ps
CPU time 1.57 seconds
Started Apr 30 02:40:49 PM PDT 24
Finished Apr 30 02:40:52 PM PDT 24
Peak memory 205344 kb
Host smart-88f32be5-29d1-476b-b0ff-e0d9ca796891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526254935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2526254935
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.686625587
Short name T11
Test name
Test status
Simulation time 215776024 ps
CPU time 1.39 seconds
Started Apr 30 02:41:00 PM PDT 24
Finished Apr 30 02:41:02 PM PDT 24
Peak memory 205332 kb
Host smart-4c5ac8b1-3df2-44b7-b673-28e17a688bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686625587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.686625587
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3647113762
Short name T25
Test name
Test status
Simulation time 107037129 ps
CPU time 0.76 seconds
Started Apr 30 02:40:58 PM PDT 24
Finished Apr 30 02:40:59 PM PDT 24
Peak memory 205168 kb
Host smart-017cfd62-ef95-49bd-baf1-7c201252896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647113762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3647113762
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1859207102
Short name T14
Test name
Test status
Simulation time 46529127 ps
CPU time 0.82 seconds
Started Apr 30 02:40:58 PM PDT 24
Finished Apr 30 02:41:00 PM PDT 24
Peak memory 213364 kb
Host smart-ca1a93ba-0f93-45f5-b5e4-33831b8c93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859207102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1859207102
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.469177090
Short name T170
Test name
Test status
Simulation time 283383960 ps
CPU time 0.89 seconds
Started Apr 30 02:40:57 PM PDT 24
Finished Apr 30 02:40:58 PM PDT 24
Peak memory 204932 kb
Host smart-d739f576-50e1-41da-945b-734b57af2c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469177090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.469177090
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.146923205
Short name T155
Test name
Test status
Simulation time 33472228 ps
CPU time 0.75 seconds
Started Apr 30 02:41:23 PM PDT 24
Finished Apr 30 02:41:24 PM PDT 24
Peak memory 205080 kb
Host smart-468c17de-4753-46df-b7c2-5cec6db89f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146923205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.146923205
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3916124509
Short name T148
Test name
Test status
Simulation time 24804624 ps
CPU time 0.76 seconds
Started Apr 30 02:41:31 PM PDT 24
Finished Apr 30 02:41:32 PM PDT 24
Peak memory 205372 kb
Host smart-880aae03-599b-4062-903a-7adb1ff8c82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916124509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3916124509
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2204600671
Short name T162
Test name
Test status
Simulation time 38426899 ps
CPU time 0.72 seconds
Started Apr 30 02:41:35 PM PDT 24
Finished Apr 30 02:41:36 PM PDT 24
Peak memory 205108 kb
Host smart-f8fa62f1-2329-4106-9f77-9b7349725001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204600671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2204600671
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2605424736
Short name T145
Test name
Test status
Simulation time 41910427 ps
CPU time 0.69 seconds
Started Apr 30 02:41:30 PM PDT 24
Finished Apr 30 02:41:31 PM PDT 24
Peak memory 205108 kb
Host smart-90d102fe-ffd0-449e-9905-dd8eebf01d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605424736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2605424736
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3925020599
Short name T135
Test name
Test status
Simulation time 53597057 ps
CPU time 0.73 seconds
Started Apr 30 02:41:29 PM PDT 24
Finished Apr 30 02:41:30 PM PDT 24
Peak memory 205160 kb
Host smart-8ca693fd-a9ee-4314-a958-c79dcc315d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925020599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3925020599
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2699377939
Short name T168
Test name
Test status
Simulation time 25435331 ps
CPU time 0.69 seconds
Started Apr 30 02:41:31 PM PDT 24
Finished Apr 30 02:41:32 PM PDT 24
Peak memory 205124 kb
Host smart-75d08d5b-b9a5-4a5f-bcbb-5735fa1c6236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699377939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2699377939
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1190431987
Short name T136
Test name
Test status
Simulation time 40721938 ps
CPU time 0.74 seconds
Started Apr 30 02:41:35 PM PDT 24
Finished Apr 30 02:41:36 PM PDT 24
Peak memory 205156 kb
Host smart-7cb365da-507c-4d24-9908-aad258cf0eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190431987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1190431987
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3890705491
Short name T46
Test name
Test status
Simulation time 41666388 ps
CPU time 0.72 seconds
Started Apr 30 02:41:36 PM PDT 24
Finished Apr 30 02:41:37 PM PDT 24
Peak memory 205148 kb
Host smart-84962d89-f9c7-4f53-854f-ac75b8c6eec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890705491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3890705491
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3219423075
Short name T29
Test name
Test status
Simulation time 11085742257 ps
CPU time 8.57 seconds
Started Apr 30 02:41:33 PM PDT 24
Finished Apr 30 02:41:42 PM PDT 24
Peak memory 213780 kb
Host smart-20e17c91-0324-413b-8ab5-190f72d63b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219423075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3219423075
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3203018726
Short name T151
Test name
Test status
Simulation time 31942790 ps
CPU time 0.71 seconds
Started Apr 30 02:41:46 PM PDT 24
Finished Apr 30 02:41:47 PM PDT 24
Peak memory 205112 kb
Host smart-4d741e6d-b988-4d45-afe8-bfb31d79fbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203018726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3203018726
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1922570476
Short name T133
Test name
Test status
Simulation time 26133449 ps
CPU time 0.72 seconds
Started Apr 30 02:40:58 PM PDT 24
Finished Apr 30 02:41:00 PM PDT 24
Peak memory 205116 kb
Host smart-d0eef7d8-4c3e-4d70-8342-eea520bc0dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922570476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1922570476
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1599326109
Short name T171
Test name
Test status
Simulation time 51111100 ps
CPU time 0.83 seconds
Started Apr 30 02:41:01 PM PDT 24
Finished Apr 30 02:41:02 PM PDT 24
Peak memory 205004 kb
Host smart-0906dc96-c0a7-496d-861a-ab582feb9c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599326109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1599326109
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2959552516
Short name T50
Test name
Test status
Simulation time 368584209 ps
CPU time 2.07 seconds
Started Apr 30 02:41:04 PM PDT 24
Finished Apr 30 02:41:06 PM PDT 24
Peak memory 229084 kb
Host smart-8c952dda-06fa-415d-b8db-9d9fffdf1c2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959552516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2959552516
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1163017850
Short name T142
Test name
Test status
Simulation time 27001373 ps
CPU time 0.72 seconds
Started Apr 30 02:41:47 PM PDT 24
Finished Apr 30 02:41:48 PM PDT 24
Peak memory 205144 kb
Host smart-82f3b701-c311-4295-b463-4fbdc4e65b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163017850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1163017850
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.79574163
Short name T13
Test name
Test status
Simulation time 3100985951 ps
CPU time 6.83 seconds
Started Apr 30 02:41:45 PM PDT 24
Finished Apr 30 02:41:53 PM PDT 24
Peak memory 205512 kb
Host smart-3ab8a086-121b-4661-ba24-40f34ed91097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79574163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.79574163
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.205078574
Short name T47
Test name
Test status
Simulation time 51011376 ps
CPU time 0.75 seconds
Started Apr 30 02:41:45 PM PDT 24
Finished Apr 30 02:41:46 PM PDT 24
Peak memory 205196 kb
Host smart-23571114-f778-4aee-b2a9-28c07e21136c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205078574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.205078574
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.52043380
Short name T117
Test name
Test status
Simulation time 61718767 ps
CPU time 0.76 seconds
Started Apr 30 02:41:45 PM PDT 24
Finished Apr 30 02:41:46 PM PDT 24
Peak memory 205152 kb
Host smart-4b98fb9c-6a12-4402-92d8-5d049fe851a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52043380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.52043380
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1653581432
Short name T141
Test name
Test status
Simulation time 244426809 ps
CPU time 0.76 seconds
Started Apr 30 02:41:48 PM PDT 24
Finished Apr 30 02:41:49 PM PDT 24
Peak memory 205172 kb
Host smart-6765b63d-b69a-4a1b-a597-0d4d13f1e3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653581432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1653581432
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1158733784
Short name T140
Test name
Test status
Simulation time 50116245 ps
CPU time 0.72 seconds
Started Apr 30 02:41:47 PM PDT 24
Finished Apr 30 02:41:48 PM PDT 24
Peak memory 205124 kb
Host smart-0a0b8681-646e-4cc1-b105-1f7e754e32e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158733784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1158733784
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.820922667
Short name T137
Test name
Test status
Simulation time 77793725 ps
CPU time 0.66 seconds
Started Apr 30 02:41:43 PM PDT 24
Finished Apr 30 02:41:44 PM PDT 24
Peak memory 205116 kb
Host smart-b62fcae2-29a9-450c-a3a0-9dd4503809bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820922667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.820922667
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2489417705
Short name T157
Test name
Test status
Simulation time 27913340 ps
CPU time 0.77 seconds
Started Apr 30 02:41:46 PM PDT 24
Finished Apr 30 02:41:47 PM PDT 24
Peak memory 205168 kb
Host smart-f98f9bf2-629d-4d4e-8fae-528862c6014f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489417705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2489417705
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3349545080
Short name T172
Test name
Test status
Simulation time 27733282 ps
CPU time 0.81 seconds
Started Apr 30 02:41:49 PM PDT 24
Finished Apr 30 02:41:50 PM PDT 24
Peak memory 205116 kb
Host smart-f7f9c6b3-d768-40b5-8781-25b8e18b3a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349545080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3349545080
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1241172633
Short name T154
Test name
Test status
Simulation time 15922756 ps
CPU time 0.76 seconds
Started Apr 30 02:41:45 PM PDT 24
Finished Apr 30 02:41:47 PM PDT 24
Peak memory 205104 kb
Host smart-a1c236e1-5574-4948-a088-3577ad9600b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241172633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1241172633
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1538228109
Short name T79
Test name
Test status
Simulation time 1279147896 ps
CPU time 4.86 seconds
Started Apr 30 02:41:45 PM PDT 24
Finished Apr 30 02:41:50 PM PDT 24
Peak memory 205364 kb
Host smart-a9f0b889-dab0-450f-82cb-a241af80a50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538228109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1538228109
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.859632774
Short name T160
Test name
Test status
Simulation time 29503218 ps
CPU time 0.77 seconds
Started Apr 30 02:41:47 PM PDT 24
Finished Apr 30 02:41:48 PM PDT 24
Peak memory 205348 kb
Host smart-42421844-342d-40c0-a1dd-3a482a526587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859632774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.859632774
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.97944375
Short name T52
Test name
Test status
Simulation time 28379045 ps
CPU time 0.72 seconds
Started Apr 30 02:41:10 PM PDT 24
Finished Apr 30 02:41:11 PM PDT 24
Peak memory 205184 kb
Host smart-b4be3375-441e-4307-a04c-94445a0b2012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97944375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.97944375
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3229061304
Short name T167
Test name
Test status
Simulation time 56487185 ps
CPU time 0.69 seconds
Started Apr 30 02:41:12 PM PDT 24
Finished Apr 30 02:41:13 PM PDT 24
Peak memory 205048 kb
Host smart-2e90e73c-bc99-4f2d-91a4-ccc864cc54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229061304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3229061304
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.4255413481
Short name T49
Test name
Test status
Simulation time 200460907 ps
CPU time 1.17 seconds
Started Apr 30 02:41:13 PM PDT 24
Finished Apr 30 02:41:15 PM PDT 24
Peak memory 237560 kb
Host smart-63f91e96-cfcc-4f67-bc3f-4453e9d1a145
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255413481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4255413481
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2856295389
Short name T54
Test name
Test status
Simulation time 64414403 ps
CPU time 0.72 seconds
Started Apr 30 02:41:56 PM PDT 24
Finished Apr 30 02:41:57 PM PDT 24
Peak memory 205132 kb
Host smart-60775c2c-7742-4936-8b4d-8c25ec1467c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856295389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2856295389
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2498692279
Short name T146
Test name
Test status
Simulation time 16188801 ps
CPU time 0.71 seconds
Started Apr 30 02:41:52 PM PDT 24
Finished Apr 30 02:41:53 PM PDT 24
Peak memory 205084 kb
Host smart-75cda451-4d0b-4920-9abc-08a9fcf31afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498692279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2498692279
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2122074994
Short name T138
Test name
Test status
Simulation time 29929587 ps
CPU time 0.74 seconds
Started Apr 30 02:41:53 PM PDT 24
Finished Apr 30 02:41:55 PM PDT 24
Peak memory 205128 kb
Host smart-99de45e9-3740-40f4-8b69-62f66493326a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122074994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2122074994
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2163711832
Short name T165
Test name
Test status
Simulation time 53871424 ps
CPU time 0.65 seconds
Started Apr 30 02:41:52 PM PDT 24
Finished Apr 30 02:41:53 PM PDT 24
Peak memory 205128 kb
Host smart-c9f88eaa-c4d1-49d8-9555-b18c593297cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163711832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2163711832
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1969772887
Short name T10
Test name
Test status
Simulation time 7002209926 ps
CPU time 2.95 seconds
Started Apr 30 02:41:53 PM PDT 24
Finished Apr 30 02:41:56 PM PDT 24
Peak memory 205484 kb
Host smart-6b80865a-a5ce-4348-94da-8f67f1d957e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969772887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1969772887
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2402599933
Short name T70
Test name
Test status
Simulation time 28721071 ps
CPU time 0.68 seconds
Started Apr 30 02:41:53 PM PDT 24
Finished Apr 30 02:41:54 PM PDT 24
Peak memory 205112 kb
Host smart-9f32f367-12c4-451c-a863-61a14a4d24d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402599933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2402599933
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1246529491
Short name T71
Test name
Test status
Simulation time 30638398 ps
CPU time 0.75 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:56 PM PDT 24
Peak memory 204820 kb
Host smart-6d6851af-060a-4b5c-9894-b55fab9516e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246529491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1246529491
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2014658432
Short name T68
Test name
Test status
Simulation time 119518366 ps
CPU time 0.74 seconds
Started Apr 30 02:41:53 PM PDT 24
Finished Apr 30 02:41:55 PM PDT 24
Peak memory 205168 kb
Host smart-736e0621-90e4-48ec-b4e6-83b783f2bf7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014658432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2014658432
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3461603508
Short name T44
Test name
Test status
Simulation time 22128134 ps
CPU time 0.73 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:55 PM PDT 24
Peak memory 205120 kb
Host smart-a333ef59-20ae-499d-9962-4ccfb211b2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461603508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3461603508
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2281792013
Short name T150
Test name
Test status
Simulation time 42909610 ps
CPU time 0.73 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:55 PM PDT 24
Peak memory 205108 kb
Host smart-8c1b7424-d1b7-4f87-bb3f-69df260ebf7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281792013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2281792013
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3928077944
Short name T144
Test name
Test status
Simulation time 24818746 ps
CPU time 0.8 seconds
Started Apr 30 02:41:13 PM PDT 24
Finished Apr 30 02:41:14 PM PDT 24
Peak memory 205164 kb
Host smart-2841319c-47d4-497f-ace6-4d4a21034da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928077944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3928077944
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2387851293
Short name T161
Test name
Test status
Simulation time 76413408 ps
CPU time 0.71 seconds
Started Apr 30 02:41:00 PM PDT 24
Finished Apr 30 02:41:02 PM PDT 24
Peak memory 205228 kb
Host smart-62810009-2bd3-46f7-b4b9-c8003b992e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387851293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2387851293
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2795300408
Short name T32
Test name
Test status
Simulation time 406029216 ps
CPU time 1.24 seconds
Started Apr 30 02:41:03 PM PDT 24
Finished Apr 30 02:41:04 PM PDT 24
Peak memory 229348 kb
Host smart-4aadf056-e8e9-43aa-a63a-7fcd65de3c3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795300408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2795300408
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.382811125
Short name T1
Test name
Test status
Simulation time 43334689 ps
CPU time 0.71 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:56 PM PDT 24
Peak memory 205176 kb
Host smart-4f5c7f45-7905-4e19-b4e8-80106a4d990e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382811125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.382811125
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1861141980
Short name T139
Test name
Test status
Simulation time 19284932 ps
CPU time 0.73 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:55 PM PDT 24
Peak memory 205136 kb
Host smart-15d86903-61e4-4468-a581-e8fc8ea42148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861141980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1861141980
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4121953244
Short name T39
Test name
Test status
Simulation time 25713738 ps
CPU time 0.78 seconds
Started Apr 30 02:41:53 PM PDT 24
Finished Apr 30 02:41:54 PM PDT 24
Peak memory 205164 kb
Host smart-f9de0919-c900-4cec-b2e5-7c8b085dec70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121953244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4121953244
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2369142934
Short name T3
Test name
Test status
Simulation time 18432396 ps
CPU time 0.71 seconds
Started Apr 30 02:41:50 PM PDT 24
Finished Apr 30 02:41:52 PM PDT 24
Peak memory 205208 kb
Host smart-9315f6f2-4dc0-4416-a631-70ad3e5558d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369142934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2369142934
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3129987183
Short name T166
Test name
Test status
Simulation time 57505333 ps
CPU time 0.71 seconds
Started Apr 30 02:41:56 PM PDT 24
Finished Apr 30 02:41:57 PM PDT 24
Peak memory 205132 kb
Host smart-3ec03893-e589-4326-948a-94b095326622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129987183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3129987183
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2460407962
Short name T134
Test name
Test status
Simulation time 30457241 ps
CPU time 0.78 seconds
Started Apr 30 02:42:02 PM PDT 24
Finished Apr 30 02:42:03 PM PDT 24
Peak memory 205168 kb
Host smart-e8c474f0-7063-4b80-aef8-ad9e02c7d4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460407962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2460407962
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.876679683
Short name T149
Test name
Test status
Simulation time 50744533 ps
CPU time 0.71 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:55 PM PDT 24
Peak memory 205112 kb
Host smart-f0bf9668-9226-4305-bd6c-c74d231a9ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876679683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.876679683
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2410397564
Short name T51
Test name
Test status
Simulation time 16683158 ps
CPU time 0.69 seconds
Started Apr 30 02:41:57 PM PDT 24
Finished Apr 30 02:41:58 PM PDT 24
Peak memory 205132 kb
Host smart-4715d237-a71a-4ccb-b876-ffc33077ce82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410397564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2410397564
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3941954031
Short name T152
Test name
Test status
Simulation time 25426461 ps
CPU time 0.72 seconds
Started Apr 30 02:41:54 PM PDT 24
Finished Apr 30 02:41:56 PM PDT 24
Peak memory 205116 kb
Host smart-109bf61a-7832-4f41-a22a-12bb6497dc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941954031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3941954031
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3064889803
Short name T17
Test name
Test status
Simulation time 2012137377 ps
CPU time 4.84 seconds
Started Apr 30 02:41:56 PM PDT 24
Finished Apr 30 02:42:01 PM PDT 24
Peak memory 205368 kb
Host smart-4236a006-e55b-4b94-8df5-3e1d63627e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064889803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3064889803
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1062880607
Short name T159
Test name
Test status
Simulation time 21959118 ps
CPU time 0.7 seconds
Started Apr 30 02:41:58 PM PDT 24
Finished Apr 30 02:41:59 PM PDT 24
Peak memory 205132 kb
Host smart-86c3b74c-f279-457d-866c-fa08b272cd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062880607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1062880607
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1720063688
Short name T158
Test name
Test status
Simulation time 19198009 ps
CPU time 0.73 seconds
Started Apr 30 02:41:05 PM PDT 24
Finished Apr 30 02:41:06 PM PDT 24
Peak memory 205164 kb
Host smart-3eb0aeff-5dd4-4ec7-bf6c-c28a305c033c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720063688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1720063688
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.269109776
Short name T55
Test name
Test status
Simulation time 610730817 ps
CPU time 2.22 seconds
Started Apr 30 02:41:14 PM PDT 24
Finished Apr 30 02:41:16 PM PDT 24
Peak memory 205472 kb
Host smart-16f24b8b-e747-43c1-9933-0ac4a4362ccb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=269109776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.269109776
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3827871079
Short name T27
Test name
Test status
Simulation time 52189789 ps
CPU time 0.73 seconds
Started Apr 30 02:41:16 PM PDT 24
Finished Apr 30 02:41:18 PM PDT 24
Peak memory 205152 kb
Host smart-ce29b230-f976-4863-9609-5f591b832049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827871079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3827871079
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3578831452
Short name T48
Test name
Test status
Simulation time 42326780 ps
CPU time 0.71 seconds
Started Apr 30 02:41:18 PM PDT 24
Finished Apr 30 02:41:19 PM PDT 24
Peak memory 205176 kb
Host smart-7d72fcb6-b419-4569-9985-54ac26366ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578831452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3578831452
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.314825290
Short name T147
Test name
Test status
Simulation time 27618071 ps
CPU time 0.79 seconds
Started Apr 30 02:41:22 PM PDT 24
Finished Apr 30 02:41:23 PM PDT 24
Peak memory 205168 kb
Host smart-b0378d8e-8a4e-4ded-8e66-7e0bb5f8bcf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314825290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.314825290
Directory /workspace/9.rv_dm_alert_test/latest
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