Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.37 93.86 81.46 87.61 74.36 82.33 98.42 37.55


Total tests in report: 310
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.43 51.43 80.77 80.77 47.53 47.53 30.17 30.17 44.87 44.87 61.83 61.83 91.55 91.55 3.27 3.27 /workspace/coverage/default/1.rv_dm_ndmreset_req.2329456451
60.49 9.07 86.05 5.29 57.55 10.03 64.40 34.23 52.56 7.69 67.00 5.17 91.97 0.42 3.91 0.64 /workspace/coverage/default/17.rv_dm_stress_all.403621331
67.20 6.71 86.56 0.50 62.09 4.53 68.99 4.59 60.26 7.69 68.67 1.67 93.24 1.27 30.64 26.73 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3856646932
72.14 4.94 90.08 3.52 67.45 5.36 76.47 7.48 70.51 10.26 74.50 5.83 94.72 1.48 31.27 0.64 /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.18143515
74.77 2.62 91.99 1.91 73.63 6.18 82.26 5.79 70.51 0.00 76.50 2.00 96.20 1.48 32.27 1.00 /workspace/coverage/default/6.rv_dm_alert_test.446693040
75.85 1.09 92.70 0.70 74.86 1.24 82.74 0.48 74.36 3.85 77.83 1.33 96.20 0.00 32.27 0.00 /workspace/coverage/default/21.rv_dm_stress_all.1352652927
76.88 1.03 92.85 0.15 77.47 2.61 83.35 0.60 74.36 0.00 78.83 1.00 96.20 0.00 35.09 2.82 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.70280447
77.26 0.38 93.00 0.15 79.67 2.20 83.51 0.16 74.36 0.00 79.00 0.17 96.20 0.00 35.09 0.00 /workspace/coverage/default/3.rv_dm_stress_all.1644723643
77.51 0.25 93.00 0.00 79.67 0.00 83.55 0.04 74.36 0.00 79.00 0.00 97.15 0.95 35.82 0.73 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.78029018
77.74 0.24 93.00 0.00 79.67 0.00 84.84 1.29 74.36 0.00 79.00 0.00 97.15 0.00 36.18 0.36 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1502337001
77.94 0.20 93.00 0.00 80.08 0.41 85.52 0.68 74.36 0.00 79.00 0.00 97.25 0.11 36.36 0.18 /workspace/coverage/default/1.rv_dm_sec_cm.1331964596
78.09 0.15 93.10 0.10 80.36 0.27 85.52 0.00 74.36 0.00 79.67 0.67 97.25 0.00 36.36 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1637394549
78.22 0.13 93.10 0.00 80.36 0.00 85.68 0.16 74.36 0.00 79.67 0.00 97.99 0.74 36.36 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1989074383
78.34 0.12 93.10 0.00 80.36 0.00 86.16 0.48 74.36 0.00 79.67 0.00 97.99 0.00 36.73 0.36 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3372691395
78.45 0.11 93.40 0.30 80.36 0.00 86.16 0.00 74.36 0.00 80.17 0.50 97.99 0.00 36.73 0.00 /workspace/coverage/default/0.rv_dm_abstractcmd_status.1829060189
78.56 0.11 93.50 0.10 80.49 0.14 86.20 0.04 74.36 0.00 80.67 0.50 97.99 0.00 36.73 0.00 /workspace/coverage/default/0.rv_dm_rom_read_access.711495269
78.66 0.10 93.71 0.20 80.49 0.00 86.20 0.00 74.36 0.00 81.17 0.50 97.99 0.00 36.73 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.3485693487
78.76 0.09 93.71 0.00 80.49 0.00 86.60 0.40 74.36 0.00 81.33 0.17 97.99 0.00 36.82 0.09 /workspace/coverage/default/36.rv_dm_alert_test.803977138
78.85 0.09 93.71 0.00 80.63 0.14 86.60 0.00 74.36 0.00 81.83 0.50 97.99 0.00 36.82 0.00 /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.262962356
78.92 0.07 93.76 0.05 80.91 0.27 86.60 0.00 74.36 0.00 82.00 0.17 97.99 0.00 36.82 0.00 /workspace/coverage/default/0.rv_dm_progbuf_busy.194171163
78.98 0.06 93.76 0.00 80.91 0.00 86.97 0.36 74.36 0.00 82.00 0.00 97.99 0.00 36.91 0.09 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.1349340030
79.04 0.06 93.76 0.00 81.04 0.14 86.97 0.00 74.36 0.00 82.00 0.00 97.99 0.00 37.18 0.27 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3683140563
79.09 0.05 93.81 0.05 81.18 0.14 86.97 0.00 74.36 0.00 82.17 0.17 97.99 0.00 37.18 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4220070028
79.14 0.05 93.86 0.05 81.32 0.14 86.97 0.00 74.36 0.00 82.33 0.17 97.99 0.00 37.18 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1433882009
79.19 0.04 93.86 0.00 81.32 0.00 87.05 0.08 74.36 0.00 82.33 0.00 98.20 0.21 37.18 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1922841563
79.23 0.04 93.86 0.00 81.32 0.00 87.13 0.08 74.36 0.00 82.33 0.00 98.42 0.21 37.18 0.00 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2985712010
79.26 0.03 93.86 0.00 81.32 0.00 87.37 0.24 74.36 0.00 82.33 0.00 98.42 0.00 37.18 0.00 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1342804725
79.29 0.03 93.86 0.00 81.32 0.00 87.49 0.12 74.36 0.00 82.33 0.00 98.42 0.00 37.27 0.09 /workspace/coverage/default/16.rv_dm_alert_test.3918933763
79.31 0.02 93.86 0.00 81.46 0.14 87.49 0.00 74.36 0.00 82.33 0.00 98.42 0.00 37.27 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1857219777
79.32 0.01 93.86 0.00 81.46 0.00 87.49 0.00 74.36 0.00 82.33 0.00 98.42 0.00 37.36 0.09 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1114402361
79.34 0.01 93.86 0.00 81.46 0.00 87.49 0.00 74.36 0.00 82.33 0.00 98.42 0.00 37.45 0.09 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3133857434
79.35 0.01 93.86 0.00 81.46 0.00 87.49 0.00 74.36 0.00 82.33 0.00 98.42 0.00 37.55 0.09 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.449538944
79.36 0.01 93.86 0.00 81.46 0.00 87.57 0.08 74.36 0.00 82.33 0.00 98.42 0.00 37.55 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3994505994
79.37 0.01 93.86 0.00 81.46 0.00 87.61 0.04 74.36 0.00 82.33 0.00 98.42 0.00 37.55 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2996097866

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2778567079
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2757624322
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3040417886
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3469485646
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.220431588
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1924255622
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3482215925
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.255891288
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3907466865
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.312404437
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4198169375
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4148499664
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2256828654
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3356848573
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2169412101
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3123125548
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2854726420
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.417336092
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1569995202
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2002212428
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2298716815
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.799762205
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3408804396
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.708597091
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1907597636
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1554913804
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2057548654
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.539065532
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.863400866
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1264796661
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3476188674
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3933400761
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1884448482
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3856420998
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2967538379
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.513433089
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1717626540
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.14305477
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1671627769
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.214879470
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.998960551
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.560923744
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3456864411
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2409021971
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4122927760
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.305674510
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.38743801
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1193665816
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1945014562
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3041011525
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3554177288
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.513716133
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3666619085
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2062161858
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2034155005
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2258417949
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3909477492
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2865172600
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3945810340
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1955133153
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1895838079
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1852163635
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2532331391
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1845706886
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1696220995
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3100572022
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3129015611
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3639293669
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4036580750
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1056195847
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2517072280
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1201401086
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2541124437
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1541878325
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2754658704
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.566391925
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1233908982
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1177523250
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2800008980
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2366420483
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2078525523
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3023419775
/workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.413715667
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1692182042
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.718536889
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2262005564
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2697700368
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1311992477
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.312079056
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2906125480
/workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.585950086
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.617120149
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2712372475
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3394126116
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.573093058
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2032187709
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3764455947
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1941457809
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.108476676
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2599591200
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2915535749
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3782278860
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3198512612
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1256803210
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.762087541
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2257270662
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4022522695
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1166937955
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.613959955
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1944908021
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1855566993
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3989762247
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2118283587
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4079970101
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3281006173
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3762796362
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2126938993
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1204990596
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3217590916
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1679652804
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1023333985
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2651097984
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1194429198
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3490273189
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.399704188
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3759010429
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.739516736
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2263569192
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.770140484
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.58782735
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.255423822
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3709486174
/workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.260068272
/workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.8471738
/workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1509016030
/workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.2757073704
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1842161063
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2665741012
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.487876367
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2545569012
/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.732294473
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2154090502
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.106222132
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.227563944
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1171223308
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2058127357
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.263285161
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.671140543
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3701500247
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1732283639
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.55937359
/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.482776091
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4064446585
/workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3692475579
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.769905151
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1127508051
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1927012275
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3754016651
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3732274942
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.121745531
/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1754035071
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.592428931
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1044072230
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2001934987
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3244906162
/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2274994865
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1836055462
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4187704352
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3933293785
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3383227927
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3245164410
/workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2510887887
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2349024610
/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3488566000
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.48765869
/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2596216081
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.763978758
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.315378249
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.795911446
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1753178246
/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.468321112
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4000994235
/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1677828665
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3330188441
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4036810514
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4020023074
/workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3615354599
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2438292793
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3720783203
/workspace/coverage/default/0.rv_dm_alert_test.2748626946
/workspace/coverage/default/0.rv_dm_cmderr_busy.3848396936
/workspace/coverage/default/0.rv_dm_cmderr_not_supported.1958999128
/workspace/coverage/default/0.rv_dm_dataaddr_rw_access.292725934
/workspace/coverage/default/0.rv_dm_hart_unavail.3918727923
/workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1273018327
/workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1159006043
/workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.918507567
/workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4083529666
/workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2492028482
/workspace/coverage/default/0.rv_dm_ndmreset_req.360000176
/workspace/coverage/default/0.rv_dm_sec_cm.3931314863
/workspace/coverage/default/0.rv_dm_smoke.2227368438
/workspace/coverage/default/0.rv_dm_tap_fsm.4065472100
/workspace/coverage/default/1.rv_dm_abstractcmd_status.1398725761
/workspace/coverage/default/1.rv_dm_alert_test.369894861
/workspace/coverage/default/1.rv_dm_cmderr_busy.2036098649
/workspace/coverage/default/1.rv_dm_cmderr_exception.3016624881
/workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3281415419
/workspace/coverage/default/1.rv_dm_cmderr_not_supported.3552783502
/workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2481923202
/workspace/coverage/default/1.rv_dm_hart_unavail.2314880138
/workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.552239149
/workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.960977205
/workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1376768093
/workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2526254935
/workspace/coverage/default/1.rv_dm_progbuf_busy.686625587
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3647113762
/workspace/coverage/default/1.rv_dm_rom_read_access.1859207102
/workspace/coverage/default/1.rv_dm_smoke.469177090
/workspace/coverage/default/10.rv_dm_alert_test.146923205
/workspace/coverage/default/11.rv_dm_alert_test.3916124509
/workspace/coverage/default/12.rv_dm_alert_test.2204600671
/workspace/coverage/default/13.rv_dm_alert_test.2605424736
/workspace/coverage/default/14.rv_dm_alert_test.3925020599
/workspace/coverage/default/15.rv_dm_alert_test.2699377939
/workspace/coverage/default/17.rv_dm_alert_test.1190431987
/workspace/coverage/default/18.rv_dm_alert_test.3890705491
/workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3219423075
/workspace/coverage/default/19.rv_dm_alert_test.3203018726
/workspace/coverage/default/2.rv_dm_alert_test.1922570476
/workspace/coverage/default/2.rv_dm_hart_unavail.1599326109
/workspace/coverage/default/2.rv_dm_sec_cm.2959552516
/workspace/coverage/default/20.rv_dm_alert_test.1163017850
/workspace/coverage/default/20.rv_dm_stress_all.79574163
/workspace/coverage/default/21.rv_dm_alert_test.205078574
/workspace/coverage/default/22.rv_dm_alert_test.52043380
/workspace/coverage/default/23.rv_dm_alert_test.1653581432
/workspace/coverage/default/24.rv_dm_alert_test.1158733784
/workspace/coverage/default/25.rv_dm_alert_test.820922667
/workspace/coverage/default/26.rv_dm_alert_test.2489417705
/workspace/coverage/default/27.rv_dm_alert_test.3349545080
/workspace/coverage/default/28.rv_dm_alert_test.1241172633
/workspace/coverage/default/28.rv_dm_stress_all.1538228109
/workspace/coverage/default/29.rv_dm_alert_test.859632774
/workspace/coverage/default/3.rv_dm_alert_test.97944375
/workspace/coverage/default/3.rv_dm_hart_unavail.3229061304
/workspace/coverage/default/3.rv_dm_sec_cm.4255413481
/workspace/coverage/default/30.rv_dm_alert_test.2856295389
/workspace/coverage/default/31.rv_dm_alert_test.2498692279
/workspace/coverage/default/32.rv_dm_alert_test.2122074994
/workspace/coverage/default/33.rv_dm_alert_test.2163711832
/workspace/coverage/default/33.rv_dm_stress_all.1969772887
/workspace/coverage/default/34.rv_dm_alert_test.2402599933
/workspace/coverage/default/35.rv_dm_alert_test.1246529491
/workspace/coverage/default/37.rv_dm_alert_test.2014658432
/workspace/coverage/default/38.rv_dm_alert_test.3461603508
/workspace/coverage/default/39.rv_dm_alert_test.2281792013
/workspace/coverage/default/4.rv_dm_alert_test.3928077944
/workspace/coverage/default/4.rv_dm_hart_unavail.2387851293
/workspace/coverage/default/4.rv_dm_sec_cm.2795300408
/workspace/coverage/default/40.rv_dm_alert_test.382811125
/workspace/coverage/default/41.rv_dm_alert_test.1861141980
/workspace/coverage/default/42.rv_dm_alert_test.4121953244
/workspace/coverage/default/43.rv_dm_alert_test.2369142934
/workspace/coverage/default/44.rv_dm_alert_test.3129987183
/workspace/coverage/default/45.rv_dm_alert_test.2460407962
/workspace/coverage/default/46.rv_dm_alert_test.876679683
/workspace/coverage/default/47.rv_dm_alert_test.2410397564
/workspace/coverage/default/48.rv_dm_alert_test.3941954031
/workspace/coverage/default/48.rv_dm_stress_all.3064889803
/workspace/coverage/default/49.rv_dm_alert_test.1062880607
/workspace/coverage/default/5.rv_dm_alert_test.1720063688
/workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.269109776
/workspace/coverage/default/7.rv_dm_alert_test.3827871079
/workspace/coverage/default/8.rv_dm_alert_test.3578831452
/workspace/coverage/default/9.rv_dm_alert_test.314825290



Total test records in report: 310
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/40.rv_dm_alert_test.382811125 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:56 PM PDT 24 43334689 ps
T2 /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.960977205 Apr 30 02:40:57 PM PDT 24 Apr 30 02:40:58 PM PDT 24 262319652 ps
T3 /workspace/coverage/default/43.rv_dm_alert_test.2369142934 Apr 30 02:41:50 PM PDT 24 Apr 30 02:41:52 PM PDT 24 18432396 ps
T27 /workspace/coverage/default/7.rv_dm_alert_test.3827871079 Apr 30 02:41:16 PM PDT 24 Apr 30 02:41:18 PM PDT 24 52189789 ps
T7 /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3281415419 Apr 30 02:40:49 PM PDT 24 Apr 30 02:40:51 PM PDT 24 84188883 ps
T4 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3552783502 Apr 30 02:40:55 PM PDT 24 Apr 30 02:41:01 PM PDT 24 2275652513 ps
T16 /workspace/coverage/default/1.rv_dm_ndmreset_req.2329456451 Apr 30 02:40:47 PM PDT 24 Apr 30 02:40:50 PM PDT 24 1381938166 ps
T31 /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.552239149 Apr 30 02:41:03 PM PDT 24 Apr 30 02:41:04 PM PDT 24 702952088 ps
T35 /workspace/coverage/default/36.rv_dm_alert_test.803977138 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:56 PM PDT 24 31540043 ps
T39 /workspace/coverage/default/42.rv_dm_alert_test.4121953244 Apr 30 02:41:53 PM PDT 24 Apr 30 02:41:54 PM PDT 24 25713738 ps
T44 /workspace/coverage/default/38.rv_dm_alert_test.3461603508 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:55 PM PDT 24 22128134 ps
T17 /workspace/coverage/default/48.rv_dm_stress_all.3064889803 Apr 30 02:41:56 PM PDT 24 Apr 30 02:42:01 PM PDT 24 2012137377 ps
T5 /workspace/coverage/default/17.rv_dm_stress_all.403621331 Apr 30 02:41:34 PM PDT 24 Apr 30 02:41:40 PM PDT 24 5064820882 ps
T6 /workspace/coverage/default/3.rv_dm_stress_all.1644723643 Apr 30 02:41:12 PM PDT 24 Apr 30 02:41:19 PM PDT 24 1568464423 ps
T45 /workspace/coverage/default/16.rv_dm_alert_test.3918933763 Apr 30 02:41:34 PM PDT 24 Apr 30 02:41:35 PM PDT 24 52993292 ps
T38 /workspace/coverage/default/6.rv_dm_alert_test.446693040 Apr 30 02:41:11 PM PDT 24 Apr 30 02:41:12 PM PDT 24 19828943 ps
T48 /workspace/coverage/default/8.rv_dm_alert_test.3578831452 Apr 30 02:41:18 PM PDT 24 Apr 30 02:41:19 PM PDT 24 42326780 ps
T28 /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.262962356 Apr 30 02:41:12 PM PDT 24 Apr 30 02:41:14 PM PDT 24 1245635401 ps
T68 /workspace/coverage/default/37.rv_dm_alert_test.2014658432 Apr 30 02:41:53 PM PDT 24 Apr 30 02:41:55 PM PDT 24 119518366 ps
T37 /workspace/coverage/default/0.rv_dm_tap_fsm.4065472100 Apr 30 02:40:44 PM PDT 24 Apr 30 02:40:49 PM PDT 24 1031436617 ps
T46 /workspace/coverage/default/18.rv_dm_alert_test.3890705491 Apr 30 02:41:36 PM PDT 24 Apr 30 02:41:37 PM PDT 24 41666388 ps
T70 /workspace/coverage/default/34.rv_dm_alert_test.2402599933 Apr 30 02:41:53 PM PDT 24 Apr 30 02:41:54 PM PDT 24 28721071 ps
T71 /workspace/coverage/default/35.rv_dm_alert_test.1246529491 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:56 PM PDT 24 30638398 ps
T32 /workspace/coverage/default/4.rv_dm_sec_cm.2795300408 Apr 30 02:41:03 PM PDT 24 Apr 30 02:41:04 PM PDT 24 406029216 ps
T18 /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.292725934 Apr 30 02:40:50 PM PDT 24 Apr 30 02:40:51 PM PDT 24 68864842 ps
T13 /workspace/coverage/default/20.rv_dm_stress_all.79574163 Apr 30 02:41:45 PM PDT 24 Apr 30 02:41:53 PM PDT 24 3100985951 ps
T47 /workspace/coverage/default/21.rv_dm_alert_test.205078574 Apr 30 02:41:45 PM PDT 24 Apr 30 02:41:46 PM PDT 24 51011376 ps
T33 /workspace/coverage/default/1.rv_dm_sec_cm.1331964596 Apr 30 02:40:58 PM PDT 24 Apr 30 02:41:00 PM PDT 24 193321556 ps
T51 /workspace/coverage/default/47.rv_dm_alert_test.2410397564 Apr 30 02:41:57 PM PDT 24 Apr 30 02:41:58 PM PDT 24 16683158 ps
T52 /workspace/coverage/default/3.rv_dm_alert_test.97944375 Apr 30 02:41:10 PM PDT 24 Apr 30 02:41:11 PM PDT 24 28379045 ps
T53 /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.918507567 Apr 30 02:40:53 PM PDT 24 Apr 30 02:40:55 PM PDT 24 108216505 ps
T54 /workspace/coverage/default/30.rv_dm_alert_test.2856295389 Apr 30 02:41:56 PM PDT 24 Apr 30 02:41:57 PM PDT 24 64414403 ps
T11 /workspace/coverage/default/1.rv_dm_progbuf_busy.686625587 Apr 30 02:41:00 PM PDT 24 Apr 30 02:41:02 PM PDT 24 215776024 ps
T156 /workspace/coverage/default/1.rv_dm_alert_test.369894861 Apr 30 02:40:56 PM PDT 24 Apr 30 02:40:57 PM PDT 24 87542821 ps
T69 /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2492028482 Apr 30 02:40:50 PM PDT 24 Apr 30 02:40:52 PM PDT 24 318597781 ps
T159 /workspace/coverage/default/49.rv_dm_alert_test.1062880607 Apr 30 02:41:58 PM PDT 24 Apr 30 02:41:59 PM PDT 24 21959118 ps
T155 /workspace/coverage/default/10.rv_dm_alert_test.146923205 Apr 30 02:41:23 PM PDT 24 Apr 30 02:41:24 PM PDT 24 33472228 ps
T157 /workspace/coverage/default/26.rv_dm_alert_test.2489417705 Apr 30 02:41:46 PM PDT 24 Apr 30 02:41:47 PM PDT 24 27913340 ps
T160 /workspace/coverage/default/29.rv_dm_alert_test.859632774 Apr 30 02:41:47 PM PDT 24 Apr 30 02:41:48 PM PDT 24 29503218 ps
T36 /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1273018327 Apr 30 02:40:49 PM PDT 24 Apr 30 02:40:51 PM PDT 24 233026247 ps
T142 /workspace/coverage/default/20.rv_dm_alert_test.1163017850 Apr 30 02:41:47 PM PDT 24 Apr 30 02:41:48 PM PDT 24 27001373 ps
T34 /workspace/coverage/default/0.rv_dm_sec_cm.3931314863 Apr 30 02:40:49 PM PDT 24 Apr 30 02:40:51 PM PDT 24 279607588 ps
T152 /workspace/coverage/default/48.rv_dm_alert_test.3941954031 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:56 PM PDT 24 25426461 ps
T29 /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3219423075 Apr 30 02:41:33 PM PDT 24 Apr 30 02:41:42 PM PDT 24 11085742257 ps
T147 /workspace/coverage/default/9.rv_dm_alert_test.314825290 Apr 30 02:41:22 PM PDT 24 Apr 30 02:41:23 PM PDT 24 27618071 ps
T148 /workspace/coverage/default/11.rv_dm_alert_test.3916124509 Apr 30 02:41:31 PM PDT 24 Apr 30 02:41:32 PM PDT 24 24804624 ps
T161 /workspace/coverage/default/4.rv_dm_hart_unavail.2387851293 Apr 30 02:41:00 PM PDT 24 Apr 30 02:41:02 PM PDT 24 76413408 ps
T145 /workspace/coverage/default/13.rv_dm_alert_test.2605424736 Apr 30 02:41:30 PM PDT 24 Apr 30 02:41:31 PM PDT 24 41910427 ps
T12 /workspace/coverage/default/0.rv_dm_abstractcmd_status.1829060189 Apr 30 02:40:55 PM PDT 24 Apr 30 02:40:57 PM PDT 24 47981924 ps
T30 /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.18143515 Apr 30 02:41:03 PM PDT 24 Apr 30 02:41:11 PM PDT 24 4357543571 ps
T116 /workspace/coverage/default/1.rv_dm_hart_unavail.2314880138 Apr 30 02:40:49 PM PDT 24 Apr 30 02:40:50 PM PDT 24 99840502 ps
T9 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1958999128 Apr 30 02:40:44 PM PDT 24 Apr 30 02:40:50 PM PDT 24 1671772962 ps
T78 /workspace/coverage/default/0.rv_dm_ndmreset_req.360000176 Apr 30 02:40:50 PM PDT 24 Apr 30 02:40:51 PM PDT 24 148561563 ps
T162 /workspace/coverage/default/12.rv_dm_alert_test.2204600671 Apr 30 02:41:35 PM PDT 24 Apr 30 02:41:36 PM PDT 24 38426899 ps
T144 /workspace/coverage/default/4.rv_dm_alert_test.3928077944 Apr 30 02:41:13 PM PDT 24 Apr 30 02:41:14 PM PDT 24 24818746 ps
T55 /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.269109776 Apr 30 02:41:14 PM PDT 24 Apr 30 02:41:16 PM PDT 24 610730817 ps
T130 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2481923202 Apr 30 02:40:55 PM PDT 24 Apr 30 02:40:57 PM PDT 24 40197780 ps
T10 /workspace/coverage/default/33.rv_dm_stress_all.1969772887 Apr 30 02:41:53 PM PDT 24 Apr 30 02:41:56 PM PDT 24 7002209926 ps
T138 /workspace/coverage/default/32.rv_dm_alert_test.2122074994 Apr 30 02:41:53 PM PDT 24 Apr 30 02:41:55 PM PDT 24 29929587 ps
T146 /workspace/coverage/default/31.rv_dm_alert_test.2498692279 Apr 30 02:41:52 PM PDT 24 Apr 30 02:41:53 PM PDT 24 16188801 ps
T49 /workspace/coverage/default/3.rv_dm_sec_cm.4255413481 Apr 30 02:41:13 PM PDT 24 Apr 30 02:41:15 PM PDT 24 200460907 ps
T163 /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1376768093 Apr 30 02:40:48 PM PDT 24 Apr 30 02:40:49 PM PDT 24 32944107 ps
T140 /workspace/coverage/default/24.rv_dm_alert_test.1158733784 Apr 30 02:41:47 PM PDT 24 Apr 30 02:41:48 PM PDT 24 50116245 ps
T136 /workspace/coverage/default/17.rv_dm_alert_test.1190431987 Apr 30 02:41:35 PM PDT 24 Apr 30 02:41:36 PM PDT 24 40721938 ps
T129 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2526254935 Apr 30 02:40:49 PM PDT 24 Apr 30 02:40:52 PM PDT 24 283557114 ps
T24 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1637394549 Apr 30 02:40:51 PM PDT 24 Apr 30 02:40:53 PM PDT 24 99617377 ps
T133 /workspace/coverage/default/2.rv_dm_alert_test.1922570476 Apr 30 02:40:58 PM PDT 24 Apr 30 02:41:00 PM PDT 24 26133449 ps
T20 /workspace/coverage/default/0.rv_dm_cmderr_busy.3848396936 Apr 30 02:40:45 PM PDT 24 Apr 30 02:40:50 PM PDT 24 2735980592 ps
T164 /workspace/coverage/default/0.rv_dm_hart_unavail.3918727923 Apr 30 02:40:52 PM PDT 24 Apr 30 02:40:54 PM PDT 24 60615316 ps
T25 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3647113762 Apr 30 02:40:58 PM PDT 24 Apr 30 02:40:59 PM PDT 24 107037129 ps
T151 /workspace/coverage/default/19.rv_dm_alert_test.3203018726 Apr 30 02:41:46 PM PDT 24 Apr 30 02:41:47 PM PDT 24 31942790 ps
T139 /workspace/coverage/default/41.rv_dm_alert_test.1861141980 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:55 PM PDT 24 19284932 ps
T165 /workspace/coverage/default/33.rv_dm_alert_test.2163711832 Apr 30 02:41:52 PM PDT 24 Apr 30 02:41:53 PM PDT 24 53871424 ps
T50 /workspace/coverage/default/2.rv_dm_sec_cm.2959552516 Apr 30 02:41:04 PM PDT 24 Apr 30 02:41:06 PM PDT 24 368584209 ps
T134 /workspace/coverage/default/45.rv_dm_alert_test.2460407962 Apr 30 02:42:02 PM PDT 24 Apr 30 02:42:03 PM PDT 24 30457241 ps
T166 /workspace/coverage/default/44.rv_dm_alert_test.3129987183 Apr 30 02:41:56 PM PDT 24 Apr 30 02:41:57 PM PDT 24 57505333 ps
T117 /workspace/coverage/default/22.rv_dm_alert_test.52043380 Apr 30 02:41:45 PM PDT 24 Apr 30 02:41:46 PM PDT 24 61718767 ps
T8 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1857219777 Apr 30 02:40:52 PM PDT 24 Apr 30 02:40:53 PM PDT 24 367647750 ps
T154 /workspace/coverage/default/28.rv_dm_alert_test.1241172633 Apr 30 02:41:45 PM PDT 24 Apr 30 02:41:47 PM PDT 24 15922756 ps
T150 /workspace/coverage/default/39.rv_dm_alert_test.2281792013 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:55 PM PDT 24 42909610 ps
T167 /workspace/coverage/default/3.rv_dm_hart_unavail.3229061304 Apr 30 02:41:12 PM PDT 24 Apr 30 02:41:13 PM PDT 24 56487185 ps
T21 /workspace/coverage/default/1.rv_dm_cmderr_busy.2036098649 Apr 30 02:40:51 PM PDT 24 Apr 30 02:40:55 PM PDT 24 3183626472 ps
T22 /workspace/coverage/default/1.rv_dm_cmderr_exception.3016624881 Apr 30 02:40:53 PM PDT 24 Apr 30 02:40:55 PM PDT 24 1527825701 ps
T168 /workspace/coverage/default/15.rv_dm_alert_test.2699377939 Apr 30 02:41:31 PM PDT 24 Apr 30 02:41:32 PM PDT 24 25435331 ps
T132 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4083529666 Apr 30 02:40:48 PM PDT 24 Apr 30 02:40:49 PM PDT 24 75485827 ps
T79 /workspace/coverage/default/28.rv_dm_stress_all.1538228109 Apr 30 02:41:45 PM PDT 24 Apr 30 02:41:50 PM PDT 24 1279147896 ps
T158 /workspace/coverage/default/5.rv_dm_alert_test.1720063688 Apr 30 02:41:05 PM PDT 24 Apr 30 02:41:06 PM PDT 24 19198009 ps
T169 /workspace/coverage/default/0.rv_dm_smoke.2227368438 Apr 30 02:40:43 PM PDT 24 Apr 30 02:40:46 PM PDT 24 982245850 ps
T135 /workspace/coverage/default/14.rv_dm_alert_test.3925020599 Apr 30 02:41:29 PM PDT 24 Apr 30 02:41:30 PM PDT 24 53597057 ps
T149 /workspace/coverage/default/46.rv_dm_alert_test.876679683 Apr 30 02:41:54 PM PDT 24 Apr 30 02:41:55 PM PDT 24 50744533 ps
T143 /workspace/coverage/default/0.rv_dm_alert_test.2748626946 Apr 30 02:40:51 PM PDT 24 Apr 30 02:40:52 PM PDT 24 27827068 ps
T137 /workspace/coverage/default/25.rv_dm_alert_test.820922667 Apr 30 02:41:43 PM PDT 24 Apr 30 02:41:44 PM PDT 24 77793725 ps
T14 /workspace/coverage/default/1.rv_dm_rom_read_access.1859207102 Apr 30 02:40:58 PM PDT 24 Apr 30 02:41:00 PM PDT 24 46529127 ps
T23 /workspace/coverage/default/0.rv_dm_cmderr_exception.3485693487 Apr 30 02:40:48 PM PDT 24 Apr 30 02:40:49 PM PDT 24 2183158772 ps
T19 /workspace/coverage/default/0.rv_dm_progbuf_busy.194171163 Apr 30 02:40:49 PM PDT 24 Apr 30 02:40:50 PM PDT 24 85902358 ps
T141 /workspace/coverage/default/23.rv_dm_alert_test.1653581432 Apr 30 02:41:48 PM PDT 24 Apr 30 02:41:49 PM PDT 24 244426809 ps
T26 /workspace/coverage/default/1.rv_dm_abstractcmd_status.1398725761 Apr 30 02:40:57 PM PDT 24 Apr 30 02:40:59 PM PDT 24 88936346 ps
T170 /workspace/coverage/default/1.rv_dm_smoke.469177090 Apr 30 02:40:57 PM PDT 24 Apr 30 02:40:58 PM PDT 24 283383960 ps
T171 /workspace/coverage/default/2.rv_dm_hart_unavail.1599326109 Apr 30 02:41:01 PM PDT 24 Apr 30 02:41:02 PM PDT 24 51111100 ps
T131 /workspace/coverage/default/21.rv_dm_stress_all.1352652927 Apr 30 02:41:44 PM PDT 24 Apr 30 02:41:50 PM PDT 24 3194654737 ps
T172 /workspace/coverage/default/27.rv_dm_alert_test.3349545080 Apr 30 02:41:49 PM PDT 24 Apr 30 02:41:50 PM PDT 24 27733282 ps
T173 /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1159006043 Apr 30 02:40:52 PM PDT 24 Apr 30 02:40:53 PM PDT 24 200350692 ps
T15 /workspace/coverage/default/0.rv_dm_rom_read_access.711495269 Apr 30 02:40:48 PM PDT 24 Apr 30 02:40:49 PM PDT 24 108808908 ps
T40 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3133857434 Apr 30 02:58:40 PM PDT 24 Apr 30 02:58:49 PM PDT 24 832112148 ps
T58 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3408804396 Apr 30 02:57:08 PM PDT 24 Apr 30 02:57:09 PM PDT 24 78720300 ps
T43 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3245164410 Apr 30 02:57:59 PM PDT 24 Apr 30 02:58:06 PM PDT 24 157343437 ps
T41 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.305674510 Apr 30 02:58:15 PM PDT 24 Apr 30 02:58:18 PM PDT 24 68939270 ps
T59 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3989762247 Apr 30 02:57:14 PM PDT 24 Apr 30 02:57:15 PM PDT 24 117176923 ps
T42 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3856646932 Apr 30 02:57:36 PM PDT 24 Apr 30 02:58:19 PM PDT 24 11632492346 ps
T89 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1922841563 Apr 30 02:57:29 PM PDT 24 Apr 30 02:57:32 PM PDT 24 568758285 ps
T60 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3383227927 Apr 30 02:57:53 PM PDT 24 Apr 30 02:57:54 PM PDT 24 68693915 ps
T65 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3244906162 Apr 30 02:57:58 PM PDT 24 Apr 30 02:58:01 PM PDT 24 225398315 ps
T66 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.70280447 Apr 30 02:58:22 PM PDT 24 Apr 30 02:58:34 PM PDT 24 534254584 ps
T174 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2967538379 Apr 30 02:58:06 PM PDT 24 Apr 30 02:58:08 PM PDT 24 154801097 ps
T72 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3945810340 Apr 30 02:58:26 PM PDT 24 Apr 30 02:58:39 PM PDT 24 6051937542 ps
T80 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4187704352 Apr 30 02:57:51 PM PDT 24 Apr 30 02:57:54 PM PDT 24 164581573 ps
T73 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2517072280 Apr 30 02:58:29 PM PDT 24 Apr 30 02:58:38 PM PDT 24 279975261 ps
T175 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4220070028 Apr 30 02:56:58 PM PDT 24 Apr 30 02:56:59 PM PDT 24 74245507 ps
T74 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1753178246 Apr 30 02:57:59 PM PDT 24 Apr 30 02:58:03 PM PDT 24 167496556 ps
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T64 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3615354599 Apr 30 02:58:04 PM PDT 24 Apr 30 02:58:25 PM PDT 24 16591974812 ps
T81 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.38743801 Apr 30 02:58:11 PM PDT 24 Apr 30 02:58:13 PM PDT 24 286591252 ps
T82 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2985712010 Apr 30 02:57:51 PM PDT 24 Apr 30 02:57:59 PM PDT 24 4295165521 ps
T75 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1671627769 Apr 30 02:58:12 PM PDT 24 Apr 30 02:58:19 PM PDT 24 3150123076 ps
T177 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1732283639 Apr 30 02:57:46 PM PDT 24 Apr 30 02:57:47 PM PDT 24 18638340 ps
T76 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3198512612 Apr 30 02:57:32 PM PDT 24 Apr 30 02:57:37 PM PDT 24 476647368 ps
T178 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2651097984 Apr 30 02:57:34 PM PDT 24 Apr 30 02:57:55 PM PDT 24 5042114220 ps
T83 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.78029018 Apr 30 02:57:13 PM PDT 24 Apr 30 02:58:13 PM PDT 24 1473936016 ps
T84 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3217590916 Apr 30 02:57:31 PM PDT 24 Apr 30 02:57:34 PM PDT 24 172115739 ps
T67 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2438292793 Apr 30 02:58:04 PM PDT 24 Apr 30 02:58:08 PM PDT 24 162414831 ps
T85 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3023419775 Apr 30 02:58:37 PM PDT 24 Apr 30 02:58:42 PM PDT 24 1485749179 ps
T179 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.263285161 Apr 30 02:57:39 PM PDT 24 Apr 30 02:57:41 PM PDT 24 452838344 ps
T77 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3469485646 Apr 30 02:57:00 PM PDT 24 Apr 30 02:57:04 PM PDT 24 131812244 ps
T112 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3683140563 Apr 30 02:58:18 PM PDT 24 Apr 30 02:58:44 PM PDT 24 6590914625 ps
T86 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2062161858 Apr 30 02:58:24 PM PDT 24 Apr 30 02:58:27 PM PDT 24 67547715 ps
T180 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4079970101 Apr 30 02:57:24 PM PDT 24 Apr 30 02:57:26 PM PDT 24 42663665 ps
T181 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.708597091 Apr 30 02:57:09 PM PDT 24 Apr 30 02:57:11 PM PDT 24 506156235 ps
T182 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2996097866 Apr 30 02:57:31 PM PDT 24 Apr 30 02:57:46 PM PDT 24 20116345930 ps
T113 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1754035071 Apr 30 02:57:52 PM PDT 24 Apr 30 02:57:54 PM PDT 24 262917897 ps
T114 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3554177288 Apr 30 02:58:13 PM PDT 24 Apr 30 02:58:16 PM PDT 24 459937908 ps
T87 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4036580750 Apr 30 02:58:29 PM PDT 24 Apr 30 02:58:34 PM PDT 24 80294672 ps
T125 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3476188674 Apr 30 02:57:09 PM PDT 24 Apr 30 02:57:18 PM PDT 24 409202939 ps
T88 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2757624322 Apr 30 02:57:03 PM PDT 24 Apr 30 02:58:01 PM PDT 24 1443933706 ps
T183 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1907597636 Apr 30 02:57:11 PM PDT 24 Apr 30 02:57:12 PM PDT 24 164891117 ps
T93 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.220431588 Apr 30 02:57:01 PM PDT 24 Apr 30 02:57:05 PM PDT 24 1294209815 ps
T153 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.1114402361 Apr 30 02:58:07 PM PDT 24 Apr 30 02:58:28 PM PDT 24 10258421929 ps
T184 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2262005564 Apr 30 02:58:40 PM PDT 24 Apr 30 02:58:46 PM PDT 24 1073769251 ps
T185 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4036810514 Apr 30 02:58:06 PM PDT 24 Apr 30 02:58:07 PM PDT 24 56032562 ps
T94 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2596216081 Apr 30 02:58:01 PM PDT 24 Apr 30 02:58:04 PM PDT 24 214640383 ps
T186 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2002212428 Apr 30 02:57:08 PM PDT 24 Apr 30 02:58:10 PM PDT 24 18489136779 ps
T187 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2032187709 Apr 30 02:58:49 PM PDT 24 Apr 30 02:58:51 PM PDT 24 514853819 ps
T188 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1509016030 Apr 30 02:58:50 PM PDT 24 Apr 30 02:59:04 PM PDT 24 6944130221 ps
T189 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3754016651 Apr 30 02:57:46 PM PDT 24 Apr 30 02:57:47 PM PDT 24 33402644 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.799762205 Apr 30 02:57:08 PM PDT 24 Apr 30 02:57:12 PM PDT 24 3250263054 ps
T115 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.718536889 Apr 30 02:58:36 PM PDT 24 Apr 30 02:58:47 PM PDT 24 4017885246 ps
T95 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2906125480 Apr 30 02:58:38 PM PDT 24 Apr 30 02:58:43 PM PDT 24 83032904 ps
T190 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.762087541 Apr 30 02:57:24 PM PDT 24 Apr 30 02:57:39 PM PDT 24 10020872383 ps
T191 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4148499664 Apr 30 02:57:00 PM PDT 24 Apr 30 02:57:01 PM PDT 24 69647237 ps
T192 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3639293669 Apr 30 02:58:26 PM PDT 24 Apr 30 02:58:28 PM PDT 24 49742316 ps
T193 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1945014562 Apr 30 02:58:12 PM PDT 24 Apr 30 02:58:14 PM PDT 24 66647269 ps
T194 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3759010429 Apr 30 02:57:34 PM PDT 24 Apr 30 02:57:37 PM PDT 24 837884520 ps
T195 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.585950086 Apr 30 02:58:41 PM PDT 24 Apr 30 02:59:06 PM PDT 24 33958388494 ps
T96 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1989074383 Apr 30 02:57:20 PM PDT 24 Apr 30 02:57:23 PM PDT 24 483242943 ps
T120 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.14305477 Apr 30 02:58:10 PM PDT 24 Apr 30 02:58:19 PM PDT 24 865466985 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1204990596 Apr 30 02:57:37 PM PDT 24 Apr 30 02:58:10 PM PDT 24 2576970082 ps
T61 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2274994865 Apr 30 02:57:52 PM PDT 24 Apr 30 02:58:01 PM PDT 24 593203043 ps
T196 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.769905151 Apr 30 02:57:53 PM PDT 24 Apr 30 02:57:59 PM PDT 24 3643126348 ps
T197 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1166937955 Apr 30 02:57:22 PM PDT 24 Apr 30 02:57:24 PM PDT 24 741761869 ps
T118 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1845706886 Apr 30 02:58:20 PM PDT 24 Apr 30 02:58:24 PM PDT 24 135242217 ps
T198 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2154090502 Apr 30 02:57:38 PM PDT 24 Apr 30 02:57:56 PM PDT 24 13956404856 ps
T199 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3933293785 Apr 30 02:57:52 PM PDT 24 Apr 30 02:57:57 PM PDT 24 1026355512 ps
T119 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2409021971 Apr 30 02:58:13 PM PDT 24 Apr 30 02:58:16 PM PDT 24 514589999 ps
T200 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2258417949 Apr 30 02:58:14 PM PDT 24 Apr 30 02:58:16 PM PDT 24 148605351 ps
T201 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1895838079 Apr 30 02:58:22 PM PDT 24 Apr 30 02:58:25 PM PDT 24 1133492420 ps
T202 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.108476676 Apr 30 02:58:42 PM PDT 24 Apr 30 02:58:48 PM PDT 24 2559352349 ps
T203 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1233908982 Apr 30 02:58:32 PM PDT 24 Apr 30 02:58:37 PM PDT 24 82859059 ps
T204 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.613959955 Apr 30 02:57:23 PM PDT 24 Apr 30 02:57:24 PM PDT 24 36308100 ps
T205 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2865172600 Apr 30 02:58:20 PM PDT 24 Apr 30 02:58:23 PM PDT 24 84964795 ps
T206 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1855566993 Apr 30 02:57:17 PM PDT 24 Apr 30 02:57:19 PM PDT 24 165278927 ps
T121 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3488566000 Apr 30 02:57:51 PM PDT 24 Apr 30 02:58:02 PM PDT 24 2319801160 ps
T207 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3933400761 Apr 30 02:58:18 PM PDT 24 Apr 30 02:58:22 PM PDT 24 136362737 ps
T208 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1127508051 Apr 30 02:57:54 PM PDT 24 Apr 30 02:57:56 PM PDT 24 200273264 ps
T209 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3709486174 Apr 30 02:57:28 PM PDT 24 Apr 30 02:57:32 PM PDT 24 321968737 ps
T97 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.795911446 Apr 30 02:58:00 PM PDT 24 Apr 30 02:58:08 PM PDT 24 548046915 ps
T210 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.48765869 Apr 30 02:57:59 PM PDT 24 Apr 30 02:58:03 PM PDT 24 42662368 ps
T211 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2001934987 Apr 30 02:57:51 PM PDT 24 Apr 30 02:57:52 PM PDT 24 138645332 ps
T212 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.770140484 Apr 30 02:57:28 PM PDT 24 Apr 30 02:57:29 PM PDT 24 18458241 ps
T109 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3909477492 Apr 30 02:58:23 PM PDT 24 Apr 30 02:58:32 PM PDT 24 918332228 ps
T213 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2298716815 Apr 30 02:57:12 PM PDT 24 Apr 30 02:58:18 PM PDT 24 19183614352 ps
T214 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2665741012 Apr 30 02:57:46 PM PDT 24 Apr 30 02:58:21 PM PDT 24 10243187963 ps
T122 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.513716133 Apr 30 02:58:14 PM PDT 24 Apr 30 02:58:33 PM PDT 24 2535893790 ps
T105 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1955133153 Apr 30 02:58:23 PM PDT 24 Apr 30 02:58:26 PM PDT 24 108279441 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3356848573 Apr 30 02:57:01 PM PDT 24 Apr 30 02:57:06 PM PDT 24 829293201 ps
T215 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.255891288 Apr 30 02:56:57 PM PDT 24 Apr 30 02:57:02 PM PDT 24 1000396385 ps
T216 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1836055462 Apr 30 02:58:01 PM PDT 24 Apr 30 02:58:04 PM PDT 24 157724031 ps
T217 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2349024610 Apr 30 02:57:54 PM PDT 24 Apr 30 02:57:59 PM PDT 24 697609022 ps
T218 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2256828654 Apr 30 02:57:01 PM PDT 24 Apr 30 02:57:02 PM PDT 24 19156393 ps
T219 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.417336092 Apr 30 02:57:16 PM PDT 24 Apr 30 02:57:21 PM PDT 24 1017143804 ps
T220 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3666619085 Apr 30 02:58:21 PM PDT 24 Apr 30 02:58:26 PM PDT 24 909167260 ps
T221 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1569995202 Apr 30 02:57:15 PM PDT 24 Apr 30 02:57:17 PM PDT 24 214105860 ps
T222 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1927012275 Apr 30 02:57:49 PM PDT 24 Apr 30 02:57:51 PM PDT 24 295716347 ps
T223 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.617120149 Apr 30 02:58:39 PM PDT 24 Apr 30 02:58:46 PM PDT 24 276051829 ps
T91 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3482215925 Apr 30 02:56:54 PM PDT 24 Apr 30 02:56:58 PM PDT 24 740946795 ps
T224 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1264796661 Apr 30 02:57:07 PM PDT 24 Apr 30 02:57:13 PM PDT 24 319502813 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.482776091 Apr 30 02:57:46 PM PDT 24 Apr 30 02:57:53 PM PDT 24 956100727 ps
T111 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4020023074 Apr 30 02:58:08 PM PDT 24 Apr 30 02:58:17 PM PDT 24 3524729419 ps
T123 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.449538944 Apr 30 02:57:48 PM PDT 24 Apr 30 02:57:57 PM PDT 24 237087419 ps
T225 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3856420998 Apr 30 02:58:06 PM PDT 24 Apr 30 02:58:09 PM PDT 24 430251846 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1842161063 Apr 30 02:57:36 PM PDT 24 Apr 30 02:58:44 PM PDT 24 2321890369 ps
T226 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2057548654 Apr 30 02:57:17 PM PDT 24 Apr 30 02:57:18 PM PDT 24 65438193 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.732294473 Apr 30 02:57:48 PM PDT 24 Apr 30 02:57:50 PM PDT 24 105282802 ps
T227 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3330188441 Apr 30 02:57:58 PM PDT 24 Apr 30 02:58:01 PM PDT 24 1132192891 ps
T228 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1044072230 Apr 30 02:57:58 PM PDT 24 Apr 30 02:58:00 PM PDT 24 457089475 ps
T229 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1193665816 Apr 30 02:58:17 PM PDT 24 Apr 30 02:58:19 PM PDT 24 306340474 ps
T230 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2754658704 Apr 30 02:58:27 PM PDT 24 Apr 30 02:58:29 PM PDT 24 49620392 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.863400866 Apr 30 02:57:16 PM PDT 24 Apr 30 02:57:21 PM PDT 24 422496236 ps
T231 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3281006173 Apr 30 02:57:33 PM PDT 24 Apr 30 02:57:42 PM PDT 24 562720135 ps
T232 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.560923744 Apr 30 02:58:07 PM PDT 24 Apr 30 02:58:08 PM PDT 24 51166426 ps
T233 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1171223308 Apr 30 02:57:38 PM PDT 24 Apr 30 02:57:40 PM PDT 24 230836731 ps
T234 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.312404437 Apr 30 02:56:57 PM PDT 24 Apr 30 02:57:01 PM PDT 24 1801503751 ps
T235 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2712372475 Apr 30 02:58:40 PM PDT 24 Apr 30 02:58:59 PM PDT 24 2945742836 ps
T236 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3490273189 Apr 30 02:57:30 PM PDT 24 Apr 30 02:57:37 PM PDT 24 1926684038 ps
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T257 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2532331391 Apr 30 02:58:27 PM PDT 24 Apr 30 02:58:36 PM PDT 24 824493287 ps
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