Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	228711	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	604274	1		T1	34		T7	12		T8	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	530828	1		T1	20		T19	16		T13	10
values[0x0]	148607	1		T1	9		T7	19		T8	6
values[0x1]	153550	1		T1	11		T7	17		T8	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173781	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	659204	1		T1	34		T7	14		T8	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4731	1		T19	1		T24	2		T50	5
valid_sources[0x01]	2973	1		T41	1		T50	2		T51	13
valid_sources[0x02]	2745	1		T18	8		T50	6		T53	27
valid_sources[0x03]	3344	1		T19	1		T13	1		T15	2
valid_sources[0x04]	3293	1		T68	4		T24	8		T50	4
valid_sources[0x05]	3906	1		T41	1		T25	2		T50	2
valid_sources[0x06]	3204	1		T19	1		T50	5		T51	47
valid_sources[0x07]	3495	1		T68	1		T24	1		T50	4
valid_sources[0x08]	2790	1		T18	3		T25	1		T137	9
valid_sources[0x09]	3437	1		T13	1		T25	5		T50	2
valid_sources[0x0a]	3545	1		T7	1		T24	2		T50	2
valid_sources[0x0b]	3244	1		T41	2		T25	4		T50	5
valid_sources[0x0c]	3272	1		T9	1		T25	2		T51	21
valid_sources[0x0d]	2926	1		T9	2		T68	1		T50	6
valid_sources[0x0e]	3599	1		T14	1		T50	8		T51	6
valid_sources[0x0f]	3393	1		T50	8		T51	3		T53	27
valid_sources[0x10]	3142	1		T15	1		T41	1		T25	1
valid_sources[0x11]	2961	1		T25	1		T50	7		T51	15
valid_sources[0x12]	2837	1		T19	1		T15	4		T50	4
valid_sources[0x13]	2944	1		T18	10		T25	2		T24	5
valid_sources[0x14]	2862	1		T68	5		T24	2		T50	9
valid_sources[0x15]	2713	1		T68	1		T24	4		T50	7
valid_sources[0x16]	3341	1		T50	12		T53	10		T46	2
valid_sources[0x17]	3415	1		T18	3		T24	2		T50	2
valid_sources[0x18]	2768	1		T25	2		T50	1		T51	18
valid_sources[0x19]	4188	1		T68	1		T50	5		T53	18
valid_sources[0x1a]	4319	1		T24	3		T51	8		T53	2
valid_sources[0x1b]	2911	1		T9	1		T50	1		T51	6
valid_sources[0x1c]	3121	1		T7	1		T50	3		T49	12
valid_sources[0x1d]	4145	1		T24	7		T50	3		T51	14
valid_sources[0x1e]	3365	1		T7	1		T50	4		T51	3
valid_sources[0x1f]	3397	1		T50	2		T51	14		T53	18
valid_sources[0x20]	6069	1		T7	1		T25	1		T50	9
valid_sources[0x21]	2945	1		T7	1		T12	3		T68	1
valid_sources[0x22]	2964	1		T20	1		T29	3		T68	1
valid_sources[0x23]	2763	1		T1	40		T25	1		T68	2
valid_sources[0x24]	3077	1		T25	4		T68	1		T50	5
valid_sources[0x25]	2779	1		T19	1		T18	1		T68	1
valid_sources[0x26]	2741	1		T50	3		T51	4		T53	46
valid_sources[0x27]	4723	1		T24	1		T50	8		T51	5
valid_sources[0x28]	3388	1		T19	1		T25	1		T51	3
valid_sources[0x29]	4428	1		T16	9		T41	1		T24	1
valid_sources[0x2a]	3233	1		T24	6		T50	3		T53	31
valid_sources[0x2b]	3579	1		T13	1		T15	2		T25	2
valid_sources[0x2c]	2975	1		T50	2		T51	6		T53	14
valid_sources[0x2d]	2570	1		T68	1		T24	3		T50	1
valid_sources[0x2e]	2813	1		T9	4		T13	1		T50	6
valid_sources[0x2f]	2573	1		T7	1		T19	1		T16	3
valid_sources[0x30]	2820	1		T28	9		T24	2		T50	5
valid_sources[0x31]	4047	1		T41	1		T25	1		T50	3
valid_sources[0x32]	4311	1		T27	2		T24	3		T51	23
valid_sources[0x33]	3672	1		T7	1		T68	1		T50	1
valid_sources[0x34]	3047	1		T25	1		T24	2		T50	7
valid_sources[0x35]	3576	1		T68	2		T24	3		T50	7
valid_sources[0x36]	3135	1		T7	1		T18	1		T50	9
valid_sources[0x37]	7477	1		T19	2		T13	1		T16	2
valid_sources[0x38]	2350	1		T50	11		T51	11		T53	23
valid_sources[0x39]	4487	1		T14	1		T50	4		T51	25
valid_sources[0x3a]	3113	1		T7	1		T25	1		T50	3
valid_sources[0x3b]	3505	1		T9	3		T16	1		T24	2
valid_sources[0x3c]	3326	1		T9	4		T18	2		T50	1
valid_sources[0x3d]	2802	1		T7	1		T9	2		T24	1
valid_sources[0x3e]	2842	1		T18	2		T50	3		T53	15
valid_sources[0x3f]	2935	1		T7	1		T24	1		T50	2
valid_sources[0x40]	2636	1		T19	1		T24	5		T50	3
valid_sources[0x41]	2878	1		T19	1		T29	1		T51	25
valid_sources[0x42]	3644	1		T24	2		T50	2		T51	9
valid_sources[0x43]	4103	1		T68	3		T50	6		T51	7
valid_sources[0x44]	3416	1		T16	1		T25	2		T138	4
valid_sources[0x45]	3439	1		T19	1		T50	2		T51	21
valid_sources[0x46]	3061	1		T19	1		T13	1		T24	3
valid_sources[0x47]	3399	1		T9	2		T50	10		T51	5
valid_sources[0x48]	3364	1		T68	1		T50	14		T51	7
valid_sources[0x49]	2747	1		T25	1		T68	1		T50	3
valid_sources[0x4a]	2877	1		T25	1		T24	9		T50	4
valid_sources[0x4b]	3399	1		T25	5		T24	2		T50	3
valid_sources[0x4c]	3154	1		T25	3		T50	2		T51	32
valid_sources[0x4d]	3177	1		T50	8		T51	11		T53	27
valid_sources[0x4e]	3243	1		T24	2		T50	3		T51	8
valid_sources[0x4f]	3288	1		T9	1		T50	6		T53	29
valid_sources[0x50]	2824	1		T137	3		T50	11		T51	3
valid_sources[0x51]	3261	1		T50	2		T51	4		T53	27
valid_sources[0x52]	4863	1		T50	6		T51	16		T53	19
valid_sources[0x53]	3379	1		T25	1		T24	1		T50	5
valid_sources[0x54]	3143	1		T25	3		T68	4		T24	5
valid_sources[0x55]	2628	1		T7	1		T50	2		T51	3
valid_sources[0x56]	3451	1		T68	2		T50	2		T51	19
valid_sources[0x57]	4202	1		T18	9		T50	2		T51	1
valid_sources[0x58]	3351	1		T24	1		T50	1		T51	11
valid_sources[0x59]	3304	1		T9	1		T16	3		T25	1
valid_sources[0x5a]	3454	1		T68	1		T50	8		T51	8
valid_sources[0x5b]	3337	1		T24	1		T50	2		T53	4
valid_sources[0x5c]	2897	1		T24	1		T50	4		T51	12
valid_sources[0x5d]	3163	1		T50	1		T51	18		T53	36
valid_sources[0x5e]	3006	1		T24	2		T50	14		T51	1
valid_sources[0x5f]	3108	1		T14	1		T15	1		T18	15
valid_sources[0x60]	2900	1		T19	1		T13	1		T24	2
valid_sources[0x61]	3240	1		T25	1		T24	1		T50	5
valid_sources[0x62]	2514	1		T68	1		T50	1		T51	7
valid_sources[0x63]	3076	1		T19	1		T18	9		T50	6
valid_sources[0x64]	3668	1		T24	1		T51	3		T53	18
valid_sources[0x65]	2912	1		T68	1		T24	4		T50	2
valid_sources[0x66]	3355	1		T41	2		T50	1		T51	22
valid_sources[0x67]	3468	1		T24	2		T50	5		T49	125
valid_sources[0x68]	3193	1		T19	2		T25	1		T51	4
valid_sources[0x69]	2752	1		T9	2		T25	2		T24	2
valid_sources[0x6a]	2983	1		T41	1		T50	4		T51	25
valid_sources[0x6b]	3625	1		T15	4		T18	1		T24	3
valid_sources[0x6c]	3203	1		T24	1		T50	3		T49	75
valid_sources[0x6d]	2744	1		T24	1		T50	1		T51	5
valid_sources[0x6e]	3081	1		T9	8		T16	3		T50	5
valid_sources[0x6f]	2756	1		T25	3		T50	1		T51	10
valid_sources[0x70]	3013	1		T18	4		T24	3		T51	17
valid_sources[0x71]	3319	1		T68	3		T50	6		T51	4
valid_sources[0x72]	3194	1		T68	1		T50	1		T51	4
valid_sources[0x73]	4428	1		T25	5		T24	7		T50	2
valid_sources[0x74]	3240	1		T18	1		T68	2		T50	1
valid_sources[0x75]	3096	1		T9	7		T41	1		T68	1
valid_sources[0x76]	3388	1		T50	1		T51	6		T53	15
valid_sources[0x77]	3178	1		T25	1		T68	1		T24	1
valid_sources[0x78]	3607	1		T18	3		T25	2		T24	1
valid_sources[0x79]	3168	1		T25	1		T24	1		T50	1
valid_sources[0x7a]	3498	1		T16	2		T27	1		T25	1
valid_sources[0x7b]	3446	1		T25	4		T50	2		T53	11
valid_sources[0x7c]	2945	1		T24	3		T50	7		T51	2
valid_sources[0x7d]	3302	1		T27	1		T29	1		T24	1
valid_sources[0x7e]	3845	1		T7	1		T15	2		T50	6
valid_sources[0x7f]	3370	1		T68	3		T50	2		T51	2
valid_sources[0x80]	2730	1		T9	1		T68	2		T50	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

311592

1

T1

14

T19

9

T13

6

values[0x0]

all_enables

biggest_size

146633

1

T1

9

T7

8

T8

4

values[0x1]

all_enables

biggest_size

146049

1

T1

11

T7

4

T8

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4910	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	20849	1		T2	3		T3	5		T5	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9820	1		T50	6		T49	96		T51	16
values[0x0]	7764	1		T2	2		T3	7		T4	2
values[0x1]	8175	1		T2	8		T3	9		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3683	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22076	1		T2	3		T3	7		T5	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	88	1		T49	2		T53	2		T46	3
valid_sources[0x01]	68	1		T139	1		T49	1		T46	3
valid_sources[0x02]	85	1		T49	2		T53	1		T83	1
valid_sources[0x03]	87	1		T46	2		T83	2		T48	1
valid_sources[0x04]	106	1		T59	1		T46	11		T81	1
valid_sources[0x05]	92	1		T63	1		T140	4		T49	3
valid_sources[0x06]	87	1		T49	1		T46	5		T83	1
valid_sources[0x07]	164	1		T141	2		T142	1		T143	12
valid_sources[0x08]	84	1		T46	3		T48	1		T67	26
valid_sources[0x09]	47	1		T46	1		T83	1		T78	3
valid_sources[0x0a]	94	1		T144	1		T49	1		T46	1
valid_sources[0x0b]	123	1		T2	1		T145	1		T49	1
valid_sources[0x0c]	103	1		T49	7		T46	9		T48	1
valid_sources[0x0d]	69	1		T45	5		T59	1		T142	2
valid_sources[0x0e]	59	1		T49	7		T53	4		T46	4
valid_sources[0x0f]	75	1		T139	1		T46	7		T83	1
valid_sources[0x10]	130	1		T140	3		T49	2		T46	2
valid_sources[0x11]	84	1		T46	4		T47	7		T78	3
valid_sources[0x12]	92	1		T146	8		T49	4		T46	4
valid_sources[0x13]	81	1		T123	20		T46	7		T78	3
valid_sources[0x14]	83	1		T46	3		T47	1		T78	4
valid_sources[0x15]	87	1		T42	1		T54	1		T46	1
valid_sources[0x16]	99	1		T49	1		T46	2		T75	15
valid_sources[0x17]	101	1		T141	1		T46	1		T83	2
valid_sources[0x18]	101	1		T49	1		T46	3		T78	1
valid_sources[0x19]	52	1		T139	1		T46	2		T48	1
valid_sources[0x1a]	73	1		T147	3		T84	1		T78	1
valid_sources[0x1b]	81	1		T49	2		T46	5		T47	3
valid_sources[0x1c]	81	1		T49	1		T46	5		T83	1
valid_sources[0x1d]	247	1		T59	1		T49	3		T46	2
valid_sources[0x1e]	60	1		T46	3		T47	7		T84	1
valid_sources[0x1f]	86	1		T49	4		T46	2		T83	2
valid_sources[0x20]	62	1		T46	7		T78	2		T79	1
valid_sources[0x21]	54	1		T46	2		T84	1		T78	3
valid_sources[0x22]	82	1		T46	4		T84	1		T78	2
valid_sources[0x23]	78	1		T145	2		T46	2		T148	15
valid_sources[0x24]	217	1		T149	1		T46	1		T67	142
valid_sources[0x25]	93	1		T53	12		T46	6		T78	1
valid_sources[0x26]	110	1		T56	2		T48	1		T78	2
valid_sources[0x27]	77	1		T53	5		T46	2		T48	2
valid_sources[0x28]	90	1		T46	3		T83	1		T48	1
valid_sources[0x29]	64	1		T139	1		T49	1		T46	1
valid_sources[0x2a]	47	1		T150	1		T46	2		T83	1
valid_sources[0x2b]	103	1		T151	2		T49	2		T46	4
valid_sources[0x2c]	78	1		T55	1		T149	4		T152	1
valid_sources[0x2d]	74	1		T49	2		T46	7		T78	4
valid_sources[0x2e]	112	1		T49	3		T47	7		T75	28
valid_sources[0x2f]	79	1		T50	2		T46	3		T83	2
valid_sources[0x30]	124	1		T46	5		T81	2		T82	3
valid_sources[0x31]	216	1		T49	3		T46	3		T67	128
valid_sources[0x32]	75	1		T49	2		T46	6		T78	1
valid_sources[0x33]	95	1		T46	1		T47	1		T84	2
valid_sources[0x34]	105	1		T59	3		T49	1		T46	1
valid_sources[0x35]	77	1		T46	6		T79	1		T81	3
valid_sources[0x36]	88	1		T44	1		T46	5		T84	1
valid_sources[0x37]	97	1		T46	3		T47	5		T78	1
valid_sources[0x38]	55	1		T49	2		T46	1		T47	1
valid_sources[0x39]	112	1		T50	1		T46	3		T47	10
valid_sources[0x3a]	188	1		T49	5		T46	1		T81	2
valid_sources[0x3b]	72	1		T49	3		T46	5		T47	9
valid_sources[0x3c]	55	1		T46	3		T84	1		T79	1
valid_sources[0x3d]	243	1		T49	1		T46	3		T75	159
valid_sources[0x3e]	96	1		T78	1		T114	4		T136	17
valid_sources[0x3f]	105	1		T45	1		T46	6		T48	1
valid_sources[0x40]	66	1		T49	6		T46	1		T47	6
valid_sources[0x41]	47	1		T49	1		T46	1		T78	1
valid_sources[0x42]	56	1		T49	4		T47	2		T78	3
valid_sources[0x43]	120	1		T76	4		T46	4		T47	3
valid_sources[0x44]	87	1		T56	2		T149	3		T53	14
valid_sources[0x45]	309	1		T119	1		T49	5		T46	2
valid_sources[0x46]	148	1		T49	2		T46	6		T75	89
valid_sources[0x47]	81	1		T46	1		T48	3		T78	4
valid_sources[0x48]	93	1		T49	2		T46	2		T47	1
valid_sources[0x49]	107	1		T49	1		T83	1		T78	1
valid_sources[0x4a]	70	1		T46	1		T78	1		T80	1
valid_sources[0x4b]	72	1		T2	1		T46	4		T48	1
valid_sources[0x4c]	75	1		T49	2		T46	2		T78	3
valid_sources[0x4d]	63	1		T150	2		T46	1		T47	1
valid_sources[0x4e]	141	1		T2	1		T76	4		T153	1
valid_sources[0x4f]	70	1		T46	3		T83	1		T48	2
valid_sources[0x50]	75	1		T59	1		T49	1		T46	1
valid_sources[0x51]	64	1		T55	1		T49	3		T46	2
valid_sources[0x52]	121	1		T59	1		T49	2		T46	3
valid_sources[0x53]	76	1		T49	2		T46	9		T83	2
valid_sources[0x54]	72	1		T142	1		T49	2		T46	2
valid_sources[0x55]	64	1		T142	1		T49	1		T46	3
valid_sources[0x56]	64	1		T83	3		T48	2		T80	4
valid_sources[0x57]	54	1		T46	4		T78	2		T115	3
valid_sources[0x58]	65	1		T49	2		T46	5		T48	1
valid_sources[0x59]	184	1		T150	1		T63	1		T139	1
valid_sources[0x5a]	86	1		T49	11		T46	5		T48	2
valid_sources[0x5b]	198	1		T154	3		T141	1		T46	3
valid_sources[0x5c]	125	1		T149	2		T139	1		T50	1
valid_sources[0x5d]	71	1		T63	1		T149	2		T142	1
valid_sources[0x5e]	74	1		T49	3		T78	5		T87	1
valid_sources[0x5f]	75	1		T49	2		T46	3		T83	2
valid_sources[0x60]	54	1		T49	1		T46	3		T48	2
valid_sources[0x61]	89	1		T145	1		T139	1		T46	4
valid_sources[0x62]	100	1		T139	1		T49	1		T46	6
valid_sources[0x63]	75	1		T141	1		T151	2		T49	1
valid_sources[0x64]	107	1		T59	1		T46	5		T48	1
valid_sources[0x65]	94	1		T153	1		T53	3		T46	3
valid_sources[0x66]	70	1		T49	2		T84	1		T78	1
valid_sources[0x67]	319	1		T46	4		T48	2		T78	3
valid_sources[0x68]	90	1		T46	4		T78	1		T79	1
valid_sources[0x69]	119	1		T49	2		T46	5		T47	1
valid_sources[0x6a]	193	1		T146	2		T147	2		T47	3
valid_sources[0x6b]	88	1		T46	4		T47	13		T78	1
valid_sources[0x6c]	84	1		T49	2		T46	1		T78	2
valid_sources[0x6d]	225	1		T45	1		T49	3		T46	4
valid_sources[0x6e]	76	1		T153	1		T149	1		T144	3
valid_sources[0x6f]	44	1		T155	1		T46	3		T48	3
valid_sources[0x70]	91	1		T42	4		T150	1		T46	3
valid_sources[0x71]	67	1		T156	2		T46	4		T78	2
valid_sources[0x72]	67	1		T49	2		T46	5		T78	5
valid_sources[0x73]	68	1		T59	1		T51	9		T53	8
valid_sources[0x74]	46	1		T157	3		T46	2		T48	1
valid_sources[0x75]	182	1		T46	2		T78	1		T82	4
valid_sources[0x76]	119	1		T119	1		T49	1		T48	1
valid_sources[0x77]	138	1		T153	1		T156	4		T46	4
valid_sources[0x78]	126	1		T145	1		T49	3		T46	3
valid_sources[0x79]	82	1		T55	1		T46	3		T83	1
valid_sources[0x7a]	64	1		T59	1		T142	1		T46	6
valid_sources[0x7b]	82	1		T49	4		T46	3		T83	1
valid_sources[0x7c]	66	1		T149	3		T46	4		T78	5
valid_sources[0x7d]	51	1		T119	1		T139	1		T50	1
valid_sources[0x7e]	70	1		T49	3		T46	1		T83	2
valid_sources[0x7f]	358	1		T59	1		T46	5		T78	4
valid_sources[0x80]	108	1		T46	5		T83	1		T84	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6995

1

T50

2

T49

91

T51

16

values[0x0]

all_enables

biggest_size

6954

1

T2

1

T3

2

T5

1

values[0x1]

all_enables

biggest_size

6900

1

T2

2

T3

3

T6

2