SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 857849 | 1 | T1 | 40 | T7 | 36 | T8 | 14 | |||
auto[1] | 18101 | 1 | T17 | 80 | T18 | 80 | T49 | 433 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 875746 | 1 | T1 | 40 | T7 | 36 | T8 | 14 | |||
values[1] | 24 | 1 | T48 | 3 | T81 | 1 | T116 | 1 | |||
values[2] | 4 | 1 | T81 | 1 | T128 | 1 | T126 | 1 | |||
values[3] | 109 | 1 | T48 | 7 | T81 | 3 | T122 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 875722 | 1 | T1 | 40 | T7 | 36 | T8 | 14 | |||
values[1] | 17 | 1 | T48 | 1 | T128 | 2 | T131 | 1 | |||
values[2] | 5 | 1 | T116 | 1 | T132 | 2 | T133 | 2 | |||
values[3] | 124 | 1 | T48 | 9 | T81 | 10 | T122 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 875640 | 1 | T1 | 40 | T7 | 36 | T8 | 14 | |||
auto[TlIntgErrCmd] | 82 | 1 | T48 | 6 | T81 | 7 | T122 | 7 | |||
auto[TlIntgErrData] | 106 | 1 | T48 | 5 | T81 | 9 | T122 | 7 | |||
auto[TlIntgErrBoth] | 122 | 1 | T48 | 9 | T81 | 4 | T122 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 42297 | 0 | T2 | 10 | T3 | 16 | T4 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 42084 | 1 | T2 | 10 | T3 | 16 | T4 | 3 | |||
values[1] | 24 | 1 | T48 | 3 | T81 | 3 | T122 | 1 | |||
values[2] | 3 | 1 | T116 | 1 | T128 | 1 | T134 | 1 | |||
values[3] | 112 | 1 | T48 | 7 | T81 | 9 | T122 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 42101 | 1 | T2 | 10 | T3 | 16 | T4 | 3 | |||
values[1] | 12 | 1 | T48 | 1 | T81 | 2 | T116 | 2 | |||
values[2] | 5 | 1 | T48 | 1 | T128 | 2 | T131 | 1 | |||
values[3] | 105 | 1 | T48 | 7 | T81 | 4 | T122 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 41987 | 1 | T2 | 10 | T3 | 16 | T4 | 3 | |||
auto[TlIntgErrCmd] | 114 | 1 | T48 | 8 | T81 | 7 | T122 | 3 | |||
auto[TlIntgErrData] | 97 | 1 | T48 | 6 | T81 | 5 | T122 | 8 | |||
auto[TlIntgErrBoth] | 99 | 1 | T48 | 6 | T81 | 8 | T122 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |