Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	270079	1		T1	6		T7	24		T8	8
full_word	605871	1		T1	34		T7	12		T8	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	875640	1		T1	40		T7	36		T8	14
auto[TlIntgErrCmd]	82	1		T48	6		T81	7		T122	7
auto[TlIntgErrData]	106	1		T48	5		T81	9		T122	7
auto[TlIntgErrBoth]	122	1		T48	9		T81	4		T122	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	532702	1		T1	20		T19	16		T13	10
auto[1]	343248	1		T1	20		T7	36		T8	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	220799	1		T1	6		T19	7		T13	4
auto[TlIntgErrNone]	partial	auto[1]	48996	1		T7	24		T8	8		T9	40
auto[TlIntgErrNone]	full_word	auto[0]	311782	1		T1	14		T19	9		T13	6
auto[TlIntgErrNone]	full_word	auto[1]	294063	1		T1	20		T7	12		T8	6
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T48	3		T81	1		T122	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T48	3		T81	6		T122	4
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T126	1		T127	1		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1		T81	5		T122	3		T116	2
auto[TlIntgErrData]	partial	auto[1]	57	1		T48	4		T81	3		T122	3
auto[TlIntgErrData]	full_word	auto[0]	8	1		T48	1		T81	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T122	1		T126	1		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T48	2		T122	2		T116	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1		T48	7		T81	2		T122	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T81	1		T116	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T81	1		T128	1		T129	1