Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.03 90.91 61.70 87.88 57.14 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 23761755 14239 0 0
late_debug_enable_rd_A 23761755 4187 0 0
late_debug_enable_regwen_rd_A 23761755 3743 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23761755 14239 0 0
T46 826750 566 0 0
T47 14883 50 0 0
T48 33817 3 0 0
T49 16648 567 0 0
T67 643201 410 0 0
T75 22868 441 0 0
T78 8200 319 0 0
T79 203492 28 0 0
T80 112661 95 0 0
T81 34878 8 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23761755 4187 0 0
T49 16648 111 0 0
T50 9309 12 0 0
T53 39907 9 0 0
T88 5469 3 0 0
T89 283039 24 0 0
T95 6882 7 0 0
T112 50550 32 0 0
T114 19604 122 0 0
T115 6435 40 0 0
T116 77638 78 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 23761755 3743 0 0
T49 16648 111 0 0
T50 9309 4 0 0
T53 39907 70 0 0
T89 283039 42 0 0
T95 6882 1 0 0
T112 50550 88 0 0
T114 19604 82 0 0
T115 6435 27 0 0
T116 77638 97 0 0
T117 18563 39 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%