Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T41,T25
11CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T41,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 11012029 11011203 0 0
selKnown1 12804439 12803613 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 11012029 11011203 0 0
T1 34384 34382 0 0
T2 310 308 0 0
T3 382 380 0 0
T4 314 312 0 0
T5 334 332 0 0
T6 384 382 0 0
T7 51474 51472 0 0
T8 13792 13790 0 0
T9 23 21 0 0
T12 2 0 0 0
T16 0 2 0 0
T19 2 0 0 0
T33 0 6 0 0
T36 8 6 0 0
T37 0 4 0 0
T38 0 40 0 0
T39 0 40 0 0
T40 0 20 0 0
T41 0 19 0 0
T42 338 336 0 0
T44 2 0 0 0
T45 410 408 0 0
T54 2 0 0 0
T56 2 0 0 0
T60 0 10 0 0
T66 0 9 0 0
T118 2 0 0 0
T119 2 0 0 0
T120 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 12804439 12803613 0 0
T1 53312 53310 0 0
T2 1893 1891 0 0
T3 2636 2634 0 0
T4 1346 1344 0 0
T5 3037 3035 0 0
T6 1826 1824 0 0
T7 111548 111546 0 0
T8 17712 17710 0 0
T9 10 8 0 0
T12 2 0 0 0
T16 0 2 0 0
T19 2 0 0 0
T33 0 6 0 0
T36 2 0 0 0
T38 0 40 0 0
T39 0 40 0 0
T40 0 20 0 0
T41 0 6 0 0
T42 2271 2269 0 0
T44 2 0 0 0
T45 2186 2184 0 0
T54 2 0 0 0
T56 2 0 0 0
T60 0 20 0 0
T61 0 20 0 0
T66 0 8 0 0
T118 2 0 0 0
T119 2 0 0 0
T120 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T41,T25
11CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T68
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1516069 1515966 0 0
selKnown1 3308614 3308511 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1516069 1515966 0 0
T1 17192 17191 0 0
T2 155 154 0 0
T3 191 190 0 0
T4 157 156 0 0
T5 167 166 0 0
T6 192 191 0 0
T7 25737 25736 0 0
T8 6896 6895 0 0
T42 169 168 0 0
T45 205 204 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3308614 3308511 0 0
T1 36120 36119 0 0
T2 1738 1737 0 0
T3 2445 2444 0 0
T4 1189 1188 0 0
T5 2870 2869 0 0
T6 1634 1633 0 0
T7 85811 85810 0 0
T8 10816 10815 0 0
T42 2102 2101 0 0
T45 1981 1980 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T41,T25
11CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T68
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 206 103 0 0
selKnown1 200 97 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 206 103 0 0
T9 11 10 0 0
T12 1 0 0 0
T16 0 1 0 0
T19 1 0 0 0
T33 0 3 0 0
T36 1 0 0 0
T37 0 2 0 0
T38 0 20 0 0
T39 0 20 0 0
T40 0 10 0 0
T41 0 2 0 0
T44 1 0 0 0
T54 1 0 0 0
T56 1 0 0 0
T60 0 10 0 0
T66 0 4 0 0
T118 1 0 0 0
T119 1 0 0 0
T120 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 200 97 0 0
T9 5 4 0 0
T12 1 0 0 0
T16 0 1 0 0
T19 1 0 0 0
T33 0 3 0 0
T36 1 0 0 0
T38 0 20 0 0
T39 0 20 0 0
T40 0 10 0 0
T41 0 3 0 0
T44 1 0 0 0
T54 1 0 0 0
T56 1 0 0 0
T60 0 10 0 0
T61 0 10 0 0
T66 0 4 0 0
T118 1 0 0 0
T119 1 0 0 0
T120 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T41,T25
11CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T41,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9494202 9493892 0 0
selKnown1 9494202 9493892 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9494202 9493892 0 0
T1 17192 17191 0 0
T2 155 154 0 0
T3 191 190 0 0
T4 157 156 0 0
T5 167 166 0 0
T6 192 191 0 0
T7 25737 25736 0 0
T8 6896 6895 0 0
T42 169 168 0 0
T45 205 204 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 9494202 9493892 0 0
T1 17192 17191 0 0
T2 155 154 0 0
T3 191 190 0 0
T4 157 156 0 0
T5 167 166 0 0
T6 192 191 0 0
T7 25737 25736 0 0
T8 6896 6895 0 0
T42 169 168 0 0
T45 205 204 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T41,T25
11CoveredT9,T41,T25

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T41,T25
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1552 1242 0 0
selKnown1 1423 1113 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1552 1242 0 0
T9 12 11 0 0
T12 1 0 0 0
T16 0 1 0 0
T19 1 0 0 0
T33 0 3 0 0
T36 7 6 0 0
T37 0 2 0 0
T38 0 20 0 0
T39 0 20 0 0
T40 0 10 0 0
T41 0 17 0 0
T44 1 0 0 0
T54 1 0 0 0
T56 1 0 0 0
T66 0 5 0 0
T118 1 0 0 0
T119 1 0 0 0
T120 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1423 1113 0 0
T9 5 4 0 0
T12 1 0 0 0
T16 0 1 0 0
T19 1 0 0 0
T33 0 3 0 0
T36 1 0 0 0
T38 0 20 0 0
T39 0 20 0 0
T40 0 10 0 0
T41 0 3 0 0
T44 1 0 0 0
T54 1 0 0 0
T56 1 0 0 0
T60 0 10 0 0
T61 0 10 0 0
T66 0 4 0 0
T118 1 0 0 0
T119 1 0 0 0
T120 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%