Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.u_lc_en_sync_copies	100.00	100.00					100.00
tb.dut.u_pm_en_sync	100.00	100.00					100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_en_sync_copies

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_pm_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.13	86.27	72.22		57.14	75.00	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.58	96.08	77.78		85.71	83.33	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_en_sync_copies

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	5	5

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_pm_en_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	618	618	0	0
OutputsKnown_A	19851684	19773138	0	0
gen_flops.OutputDelay_A	9925842	9884769	0	927
gen_no_flops.OutputDelay_A	9925842	9886569	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618	618	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T42	6	6	0	0
T45	6	6	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19851684	19773138	0	0
T1	216720	216354	0	0
T2	10428	10080	0	0
T3	14670	14244	0	0
T4	7134	6774	0	0
T5	17220	16920	0	0
T6	9804	9408	0	0
T7	514866	514560	0	0
T8	64896	64434	0	0
T42	12612	12270	0	0
T45	11886	11490	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9925842	9884769	0	927
T1	108360	108168	0	9
T2	5214	5031	0	9
T3	7335	7113	0	9
T4	3567	3378	0	9
T5	8610	8451	0	9
T6	4902	4695	0	9
T7	257433	257271	0	9
T8	32448	32208	0	9
T42	6306	6126	0	9
T45	5943	5736	0	9

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9925842	9886569	0	0
T1	108360	108177	0	0
T2	5214	5040	0	0
T3	7335	7122	0	0
T4	3567	3387	0	0
T5	8610	8460	0	0
T6	4902	4704	0	0
T7	257433	257280	0	0
T8	32448	32217	0	0
T42	6306	6135	0	0
T45	5943	5745	0	0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	103	103	0	0
OutputsKnown_A	3308614	3295523	0	0
gen_flops.OutputDelay_A	3308614	3294923	0	309

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T42	1	1	0	0
T45	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3294923	0	309
T1	36120	36056	0	3
T2	1738	1677	0	3
T3	2445	2371	0	3
T4	1189	1126	0	3
T5	2870	2817	0	3
T6	1634	1565	0	3
T7	85811	85757	0	3
T8	10816	10736	0	3
T42	2102	2042	0	3
T45	1981	1912	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	103	103	0	0
OutputsKnown_A	3308614	3295523	0	0
gen_flops.OutputDelay_A	3308614	3294923	0	309

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T42	1	1	0	0
T45	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3294923	0	309
T1	36120	36056	0	3
T2	1738	1677	0	3
T3	2445	2371	0	3
T4	1189	1126	0	3
T5	2870	2817	0	3
T6	1634	1565	0	3
T7	85811	85757	0	3
T8	10816	10736	0	3
T42	2102	2042	0	3
T45	1981	1912	0	3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	5	5

---

Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	103	103	0	0
OutputsKnown_A	3308614	3295523	0	0
gen_no_flops.OutputDelay_A	3308614	3295523	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T42	1	1	0	0
T45	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

Line Coverage for Instance : tb.dut.u_pm_en_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.u_pm_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	103	103	0	0
OutputsKnown_A	3308614	3295523	0	0
gen_flops.OutputDelay_A	3308614	3294923	0	309

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T42	1	1	0	0
T45	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3294923	0	309
T1	36120	36056	0	3
T2	1738	1677	0	3
T3	2445	2371	0	3
T4	1189	1126	0	3
T5	2870	2817	0	3
T6	1634	1565	0	3
T7	85811	85757	0	3
T8	10816	10736	0	3
T42	2102	2042	0	3
T45	1981	1912	0	3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	103	103	0	0
OutputsKnown_A	3308614	3295523	0	0
gen_no_flops.OutputDelay_A	3308614	3295523	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T42	1	1	0	0
T45	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	103	103	0	0
OutputsKnown_A	3308614	3295523	0	0
gen_no_flops.OutputDelay_A	3308614	3295523	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T42	1	1	0	0
T45	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3308614	3295523	0	0
T1	36120	36059	0	0
T2	1738	1680	0	0
T3	2445	2374	0	0
T4	1189	1129	0	0
T5	2870	2820	0	0
T6	1634	1568	0	0
T7	85811	85760	0	0
T8	10816	10739	0	0
T42	2102	2045	0	0
T45	1981	1915	0	0