Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181322	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	535592	1		T1	2		T3	3		T5	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	436557	1		T3	2		T6	20		T15	80
values[0x0]	137735	1		T3	2		T5	5		T6	26
values[0x1]	142622	1		T1	2		T5	3		T6	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139496	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	577418	1		T1	2		T3	4		T5	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2519	1		T20	1		T128	1		T41	1
valid_sources[0x01]	2551	1		T7	1		T18	4		T19	1
valid_sources[0x02]	2358	1		T41	3		T42	11		T40	1
valid_sources[0x03]	2692	1		T34	1		T42	9		T43	18
valid_sources[0x04]	2435	1		T15	1		T7	3		T10	5
valid_sources[0x05]	2759	1		T15	1		T14	1		T41	1
valid_sources[0x06]	3886	1		T15	1		T34	1		T129	1
valid_sources[0x07]	2235	1		T15	1		T7	1		T41	1
valid_sources[0x08]	2274	1		T15	1		T34	3		T16	2
valid_sources[0x09]	3177	1		T9	1		T110	1		T128	1
valid_sources[0x0a]	2461	1		T6	1		T42	11		T75	3
valid_sources[0x0b]	2805	1		T14	2		T42	13		T68	50
valid_sources[0x0c]	3066	1		T6	1		T20	1		T14	1
valid_sources[0x0d]	3270	1		T6	1		T14	1		T42	14
valid_sources[0x0e]	2725	1		T14	1		T38	10		T39	3
valid_sources[0x0f]	2564	1		T39	11		T42	9		T43	28
valid_sources[0x10]	2723	1		T15	1		T7	1		T9	3
valid_sources[0x11]	3156	1		T6	3		T15	1		T14	2
valid_sources[0x12]	2626	1		T15	1		T19	2		T39	6
valid_sources[0x13]	2682	1		T14	1		T128	1		T41	1
valid_sources[0x14]	2661	1		T14	1		T39	5		T42	10
valid_sources[0x15]	3257	1		T15	2		T39	2		T42	2
valid_sources[0x16]	3391	1		T7	1		T21	9		T42	11
valid_sources[0x17]	2781	1		T20	1		T41	1		T42	26
valid_sources[0x18]	2821	1		T42	13		T40	6		T67	4
valid_sources[0x19]	2890	1		T15	2		T42	17		T40	1
valid_sources[0x1a]	2999	1		T7	1		T19	2		T14	2
valid_sources[0x1b]	3008	1		T6	4		T34	2		T42	9
valid_sources[0x1c]	3426	1		T6	4		T14	1		T39	13
valid_sources[0x1d]	2596	1		T7	2		T13	2		T128	1
valid_sources[0x1e]	3135	1		T128	1		T41	2		T42	14
valid_sources[0x1f]	2864	1		T42	10		T40	1		T67	8
valid_sources[0x20]	3298	1		T15	1		T42	7		T40	2
valid_sources[0x21]	2884	1		T6	2		T34	1		T14	1
valid_sources[0x22]	2925	1		T6	1		T13	1		T128	1
valid_sources[0x23]	2657	1		T9	1		T14	1		T41	1
valid_sources[0x24]	2628	1		T14	1		T129	1		T42	16
valid_sources[0x25]	3165	1		T9	4		T19	2		T129	1
valid_sources[0x26]	2661	1		T6	2		T15	1		T7	1
valid_sources[0x27]	2810	1		T128	1		T42	16		T75	4
valid_sources[0x28]	3287	1		T9	1		T41	1		T39	2
valid_sources[0x29]	3248	1		T6	1		T15	1		T34	1
valid_sources[0x2a]	3118	1		T15	1		T7	1		T34	1
valid_sources[0x2b]	3545	1		T15	1		T42	6		T40	2
valid_sources[0x2c]	2567	1		T7	1		T41	2		T39	9
valid_sources[0x2d]	3316	1		T6	1		T7	1		T41	1
valid_sources[0x2e]	3065	1		T15	1		T10	3		T19	1
valid_sources[0x2f]	2763	1		T6	2		T7	1		T42	9
valid_sources[0x30]	3156	1		T11	3		T19	1		T128	1
valid_sources[0x31]	2851	1		T6	1		T34	1		T129	1
valid_sources[0x32]	2607	1		T6	2		T15	1		T42	5
valid_sources[0x33]	2766	1		T15	1		T38	15		T41	1
valid_sources[0x34]	2808	1		T42	7		T75	2		T68	37
valid_sources[0x35]	2723	1		T15	1		T14	1		T41	1
valid_sources[0x36]	2592	1		T7	2		T10	10		T14	3
valid_sources[0x37]	3863	1		T7	1		T34	1		T14	5
valid_sources[0x38]	2863	1		T9	4		T13	1		T128	1
valid_sources[0x39]	2674	1		T6	3		T15	2		T7	1
valid_sources[0x3a]	2998	1		T7	1		T41	1		T42	8
valid_sources[0x3b]	2638	1		T6	1		T34	1		T14	5
valid_sources[0x3c]	2257	1		T15	1		T11	1		T34	1
valid_sources[0x3d]	2762	1		T7	1		T41	1		T42	1
valid_sources[0x3e]	2764	1		T6	1		T15	1		T34	1
valid_sources[0x3f]	3317	1		T7	1		T129	1		T23	1
valid_sources[0x40]	2414	1		T34	1		T42	10		T75	2
valid_sources[0x41]	2868	1		T6	1		T41	1		T42	9
valid_sources[0x42]	2868	1		T7	1		T39	137		T42	1
valid_sources[0x43]	2518	1		T14	2		T39	9		T42	10
valid_sources[0x44]	2726	1		T7	1		T19	3		T38	1
valid_sources[0x45]	2575	1		T14	3		T42	7		T75	3
valid_sources[0x46]	2689	1		T7	1		T41	1		T42	12
valid_sources[0x47]	2436	1		T39	6		T42	10		T68	48
valid_sources[0x48]	2729	1		T129	1		T41	2		T42	8
valid_sources[0x49]	2467	1		T7	1		T130	40		T41	2
valid_sources[0x4a]	2417	1		T15	1		T16	11		T41	1
valid_sources[0x4b]	2912	1		T34	2		T128	1		T41	1
valid_sources[0x4c]	2612	1		T7	2		T18	4		T14	2
valid_sources[0x4d]	3034	1		T18	4		T42	11		T75	1
valid_sources[0x4e]	2572	1		T7	1		T41	1		T42	12
valid_sources[0x4f]	2656	1		T45	1		T41	1		T42	9
valid_sources[0x50]	2685	1		T34	1		T41	2		T39	2
valid_sources[0x51]	3222	1		T6	1		T15	2		T23	1
valid_sources[0x52]	2208	1		T129	2		T39	2		T42	17
valid_sources[0x53]	2838	1		T7	3		T14	2		T129	1
valid_sources[0x54]	2222	1		T41	1		T42	2		T75	2
valid_sources[0x55]	2907	1		T18	6		T16	1		T42	26
valid_sources[0x56]	2973	1		T23	1		T39	14		T42	21
valid_sources[0x57]	2682	1		T42	9		T40	23		T75	3
valid_sources[0x58]	2602	1		T6	1		T7	2		T12	1
valid_sources[0x59]	2689	1		T1	1		T39	1		T42	6
valid_sources[0x5a]	2658	1		T7	1		T34	1		T14	1
valid_sources[0x5b]	2420	1		T9	2		T14	4		T42	7
valid_sources[0x5c]	2207	1		T6	2		T34	1		T14	2
valid_sources[0x5d]	2900	1		T15	1		T7	1		T34	1
valid_sources[0x5e]	3307	1		T15	1		T7	1		T42	19
valid_sources[0x5f]	2394	1		T7	1		T38	14		T41	2
valid_sources[0x60]	2994	1		T42	21		T75	2		T68	38
valid_sources[0x61]	2495	1		T13	2		T34	1		T14	2
valid_sources[0x62]	2518	1		T3	3		T7	1		T19	1
valid_sources[0x63]	2903	1		T7	1		T42	12		T75	5
valid_sources[0x64]	2543	1		T6	1		T12	2		T129	1
valid_sources[0x65]	2576	1		T6	4		T7	1		T9	3
valid_sources[0x66]	2928	1		T15	1		T34	2		T110	2
valid_sources[0x67]	2420	1		T15	1		T7	1		T42	7
valid_sources[0x68]	3202	1		T15	1		T42	15		T43	73
valid_sources[0x69]	2958	1		T10	7		T14	1		T39	2
valid_sources[0x6a]	2436	1		T13	2		T41	3		T42	11
valid_sources[0x6b]	2266	1		T15	2		T11	2		T128	1
valid_sources[0x6c]	3473	1		T41	1		T42	14		T74	44
valid_sources[0x6d]	3213	1		T7	2		T41	1		T42	12
valid_sources[0x6e]	2631	1		T6	2		T12	1		T19	1
valid_sources[0x6f]	4189	1		T129	1		T41	2		T42	19
valid_sources[0x70]	2609	1		T6	1		T15	1		T7	1
valid_sources[0x71]	2982	1		T15	1		T14	2		T42	1
valid_sources[0x72]	3034	1		T14	5		T42	11		T43	275
valid_sources[0x73]	2681	1		T15	1		T7	1		T34	1
valid_sources[0x74]	2679	1		T34	1		T42	12		T74	47
valid_sources[0x75]	2643	1		T11	2		T34	1		T39	22
valid_sources[0x76]	2769	1		T6	3		T7	2		T128	1
valid_sources[0x77]	3140	1		T19	3		T128	1		T42	10
valid_sources[0x78]	2665	1		T6	2		T7	1		T13	3
valid_sources[0x79]	2557	1		T15	1		T18	2		T14	1
valid_sources[0x7a]	3123	1		T15	2		T7	1		T10	18
valid_sources[0x7b]	3909	1		T6	1		T12	1		T22	2
valid_sources[0x7c]	2530	1		T11	1		T42	18		T74	1
valid_sources[0x7d]	3251	1		T1	1		T128	1		T41	1
valid_sources[0x7e]	2520	1		T9	1		T17	3		T41	1
valid_sources[0x7f]	2795	1		T11	2		T14	1		T41	4
valid_sources[0x80]	2572	1		T6	2		T14	4		T128	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

263811

1

T3

1

T6

11

T15

80

values[0x0]

all_enables

biggest_size

135923

1

T3

2

T5

3

T6

13

values[0x1]

all_enables

biggest_size

135858

1

T1

2

T5

1

T6

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4666	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	22782	1		T4	4		T32	9		T33	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10024	1		T38	103		T41	40		T39	278
values[0x0]	8524	1		T4	4		T32	12		T33	5
values[0x1]	8900	1		T2	1		T4	7		T32	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3556	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	23892	1		T4	5		T32	10		T33	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75	1		T33	1		T131	1		T132	1
valid_sources[0x01]	168	1		T133	1		T111	3		T39	4
valid_sources[0x02]	54	1		T44	3		T39	7		T43	1
valid_sources[0x03]	57	1		T36	4		T134	1		T39	3
valid_sources[0x04]	102	1		T39	4		T40	6		T68	1
valid_sources[0x05]	74	1		T135	1		T39	6		T40	6
valid_sources[0x06]	48	1		T39	7		T42	1		T40	2
valid_sources[0x07]	74	1		T51	5		T39	12		T40	1
valid_sources[0x08]	58	1		T39	4		T68	1		T136	1
valid_sources[0x09]	64	1		T113	1		T137	11		T138	1
valid_sources[0x0a]	69	1		T132	1		T134	1		T39	5
valid_sources[0x0b]	68	1		T56	1		T131	1		T39	1
valid_sources[0x0c]	62	1		T139	1		T39	3		T40	4
valid_sources[0x0d]	81	1		T39	4		T40	3		T68	1
valid_sources[0x0e]	72	1		T41	4		T39	3		T40	1
valid_sources[0x0f]	76	1		T131	2		T140	1		T39	3
valid_sources[0x10]	201	1		T132	1		T39	4		T40	6
valid_sources[0x11]	72	1		T32	4		T40	6		T43	1
valid_sources[0x12]	49	1		T39	1		T42	1		T40	5
valid_sources[0x13]	38	1		T39	5		T40	1		T73	1
valid_sources[0x14]	89	1		T48	1		T39	5		T40	3
valid_sources[0x15]	71	1		T141	1		T39	1		T42	1
valid_sources[0x16]	80	1		T44	1		T39	5		T40	8
valid_sources[0x17]	211	1		T41	14		T39	2		T40	5
valid_sources[0x18]	80	1		T142	4		T143	1		T144	2
valid_sources[0x19]	51	1		T52	1		T39	5		T40	2
valid_sources[0x1a]	143	1		T39	9		T40	2		T43	1
valid_sources[0x1b]	84	1		T133	2		T41	5		T39	2
valid_sources[0x1c]	82	1		T32	4		T39	5		T40	3
valid_sources[0x1d]	82	1		T39	4		T40	4		T43	1
valid_sources[0x1e]	112	1		T46	2		T145	1		T138	1
valid_sources[0x1f]	111	1		T48	1		T132	1		T39	8
valid_sources[0x20]	100	1		T56	1		T39	2		T42	1
valid_sources[0x21]	83	1		T49	2		T39	7		T40	2
valid_sources[0x22]	68	1		T39	3		T42	1		T40	2
valid_sources[0x23]	63	1		T39	5		T40	3		T43	4
valid_sources[0x24]	196	1		T39	10		T40	4		T68	1
valid_sources[0x25]	189	1		T37	1		T39	1		T40	9
valid_sources[0x26]	119	1		T39	2		T40	4		T117	2
valid_sources[0x27]	105	1		T134	1		T39	3		T40	3
valid_sources[0x28]	91	1		T141	1		T39	3		T40	1
valid_sources[0x29]	77	1		T39	4		T43	1		T68	2
valid_sources[0x2a]	133	1		T52	2		T39	3		T40	1
valid_sources[0x2b]	70	1		T39	3		T40	2		T68	1
valid_sources[0x2c]	63	1		T56	2		T39	7		T40	2
valid_sources[0x2d]	133	1		T49	1		T39	4		T40	4
valid_sources[0x2e]	85	1		T44	2		T39	5		T40	6
valid_sources[0x2f]	132	1		T135	1		T39	4		T40	6
valid_sources[0x30]	98	1		T146	2		T41	3		T39	6
valid_sources[0x31]	105	1		T39	4		T42	1		T40	7
valid_sources[0x32]	53	1		T39	2		T40	1		T68	1
valid_sources[0x33]	232	1		T39	2		T42	1		T40	5
valid_sources[0x34]	408	1		T49	2		T145	1		T134	1
valid_sources[0x35]	86	1		T33	1		T48	1		T131	1
valid_sources[0x36]	167	1		T133	1		T39	4		T43	2
valid_sources[0x37]	94	1		T39	7		T40	1		T43	2
valid_sources[0x38]	64	1		T39	8		T40	5		T73	1
valid_sources[0x39]	80	1		T39	2		T40	6		T136	2
valid_sources[0x3a]	62	1		T146	1		T39	7		T40	2
valid_sources[0x3b]	85	1		T147	1		T39	5		T40	3
valid_sources[0x3c]	251	1		T41	1		T39	7		T40	3
valid_sources[0x3d]	83	1		T113	2		T39	4		T68	1
valid_sources[0x3e]	58	1		T39	4		T79	1		T117	2
valid_sources[0x3f]	102	1		T39	7		T42	3		T68	1
valid_sources[0x40]	41	1		T140	1		T39	1		T40	5
valid_sources[0x41]	64	1		T132	1		T40	3		T43	1
valid_sources[0x42]	94	1		T41	1		T39	3		T40	4
valid_sources[0x43]	215	1		T41	4		T39	7		T40	4
valid_sources[0x44]	65	1		T39	3		T40	2		T43	1
valid_sources[0x45]	59	1		T4	1		T46	1		T134	1
valid_sources[0x46]	66	1		T39	6		T42	1		T40	4
valid_sources[0x47]	75	1		T141	1		T39	1		T40	2
valid_sources[0x48]	144	1		T56	2		T135	1		T39	8
valid_sources[0x49]	66	1		T46	9		T139	2		T39	3
valid_sources[0x4a]	57	1		T39	3		T42	1		T40	1
valid_sources[0x4b]	101	1		T39	6		T40	2		T43	2
valid_sources[0x4c]	53	1		T39	2		T40	5		T68	1
valid_sources[0x4d]	61	1		T140	1		T39	4		T40	2
valid_sources[0x4e]	58	1		T48	1		T39	2		T40	1
valid_sources[0x4f]	178	1		T41	9		T39	2		T40	4
valid_sources[0x50]	52	1		T39	7		T40	5		T68	1
valid_sources[0x51]	134	1		T148	1		T41	1		T39	1
valid_sources[0x52]	141	1		T4	1		T33	1		T39	4
valid_sources[0x53]	283	1		T41	2		T39	4		T40	5
valid_sources[0x54]	265	1		T113	2		T39	8		T40	5
valid_sources[0x55]	142	1		T32	4		T44	4		T133	2
valid_sources[0x56]	74	1		T135	1		T39	4		T40	1
valid_sources[0x57]	76	1		T33	1		T65	7		T39	2
valid_sources[0x58]	81	1		T39	4		T40	6		T68	1
valid_sources[0x59]	109	1		T39	3		T42	1		T40	6
valid_sources[0x5a]	64	1		T49	1		T134	1		T40	2
valid_sources[0x5b]	130	1		T52	1		T149	1		T150	16
valid_sources[0x5c]	71	1		T135	1		T49	1		T131	1
valid_sources[0x5d]	101	1		T113	1		T39	1		T40	1
valid_sources[0x5e]	94	1		T139	1		T39	6		T40	6
valid_sources[0x5f]	58	1		T37	3		T39	6		T40	1
valid_sources[0x60]	149	1		T39	3		T40	3		T43	1
valid_sources[0x61]	86	1		T132	2		T142	6		T39	3
valid_sources[0x62]	209	1		T131	1		T39	10		T42	1
valid_sources[0x63]	83	1		T131	1		T39	4		T40	2
valid_sources[0x64]	118	1		T39	2		T40	1		T43	3
valid_sources[0x65]	76	1		T44	2		T139	1		T134	1
valid_sources[0x66]	64	1		T133	1		T139	1		T39	6
valid_sources[0x67]	53	1		T134	1		T39	8		T40	4
valid_sources[0x68]	75	1		T46	2		T151	9		T39	2
valid_sources[0x69]	59	1		T149	1		T39	3		T40	2
valid_sources[0x6a]	81	1		T4	1		T39	5		T40	4
valid_sources[0x6b]	81	1		T133	1		T144	5		T39	3
valid_sources[0x6c]	93	1		T152	3		T39	9		T42	1
valid_sources[0x6d]	516	1		T47	10		T52	1		T39	5
valid_sources[0x6e]	132	1		T153	12		T149	1		T39	3
valid_sources[0x6f]	103	1		T39	3		T42	3		T40	5
valid_sources[0x70]	119	1		T142	5		T38	64		T39	1
valid_sources[0x71]	87	1		T142	2		T148	1		T40	6
valid_sources[0x72]	74	1		T141	1		T39	9		T42	1
valid_sources[0x73]	95	1		T36	1		T134	1		T39	2
valid_sources[0x74]	82	1		T56	1		T50	1		T39	2
valid_sources[0x75]	172	1		T39	8		T40	1		T68	2
valid_sources[0x76]	57	1		T39	1		T40	5		T43	2
valid_sources[0x77]	50	1		T39	3		T40	3		T73	2
valid_sources[0x78]	146	1		T32	6		T154	5		T149	1
valid_sources[0x79]	63	1		T44	1		T39	3		T40	6
valid_sources[0x7a]	66	1		T39	2		T42	3		T40	3
valid_sources[0x7b]	48	1		T155	1		T140	1		T39	3
valid_sources[0x7c]	72	1		T39	4		T40	3		T68	1
valid_sources[0x7d]	46	1		T39	6		T40	2		T68	1
valid_sources[0x7e]	82	1		T41	8		T39	5		T40	3
valid_sources[0x7f]	112	1		T139	1		T39	1		T40	3
valid_sources[0x80]	67	1		T39	4		T40	2		T68	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7320

1

T38

103

T41

39

T39

272

values[0x0]

all_enables

biggest_size

7765

1

T4

2

T32

6

T33

2

values[0x1]

all_enables

biggest_size

7697

1

T4

2

T32

3

T56

1