Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 220906 1 T3 1 T5 4 T6 40
full_word 537242 1 T1 2 T3 3 T5 4



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 757848 1 T1 2 T3 4 T5 8
auto[TlIntgErrCmd] 95 1 T43 4 T68 8 T112 1
auto[TlIntgErrData] 107 1 T43 8 T68 6 T112 5
auto[TlIntgErrBoth] 98 1 T43 8 T68 6 T112 4



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 438461 1 T3 2 T6 20 T15 80
auto[1] 319687 1 T1 2 T3 2 T5 8



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 174335 1 T3 1 T6 9 T7 13
auto[TlIntgErrNone] partial auto[1] 46293 1 T5 4 T6 31 T7 45
auto[TlIntgErrNone] full_word auto[0] 263994 1 T3 1 T6 11 T15 80
auto[TlIntgErrNone] full_word auto[1] 273226 1 T1 2 T3 2 T5 4
auto[TlIntgErrCmd] partial auto[0] 31 1 T43 1 T68 2 T117 3
auto[TlIntgErrCmd] partial auto[1] 58 1 T43 3 T68 5 T112 1
auto[TlIntgErrCmd] full_word auto[0] 2 1 T68 1 T123 1 - -
auto[TlIntgErrCmd] full_word auto[1] 4 1 T121 1 T124 1 T125 1
auto[TlIntgErrData] partial auto[0] 54 1 T43 4 T68 3 T112 3
auto[TlIntgErrData] partial auto[1] 45 1 T43 3 T68 3 T112 2
auto[TlIntgErrData] full_word auto[0] 3 1 T43 1 T118 1 T126 1
auto[TlIntgErrData] full_word auto[1] 5 1 T122 1 T123 1 T127 2
auto[TlIntgErrBoth] partial auto[0] 38 1 T43 1 T68 4 T112 3
auto[TlIntgErrBoth] partial auto[1] 52 1 T43 6 T68 2 T112 1
auto[TlIntgErrBoth] full_word auto[0] 4 1 T117 2 T121 1 T119 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T43 1 T125 1 T127 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%