Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	33353269	13815	0	0
late_debug_enable_rd_A	33353269	3363	0	0
late_debug_enable_regwen_rd_A	33353269	3256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33353269	13815	0	0
T38	747859	115	0	0
T39	597682	757	0	0
T40	138969	284	0	0
T41	8463	166	0	0
T43	84211	6	0	0
T67	6073	685	0	0
T68	41411	5	0	0
T69	190548	17	0	0
T70	18672	657	0	0
T71	15704	251	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33353269	3363	0	0
T41	8463	106	0	0
T42	27892	8	0	0
T43	84211	106	0	0
T60	23959	66	0	0
T69	190548	22	0	0
T73	15372	67	0	0
T77	20213	42	0	0
T80	19946	3	0	0
T81	633562	457	0	0
T82	49250	20	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33353269	3256	0	0
T41	8463	75	0	0
T42	27892	37	0	0
T43	84211	97	0	0
T60	23959	47	0	0
T69	190548	38	0	0
T73	15372	82	0	0
T77	20213	15	0	0
T81	633562	410	0	0
T82	49250	38	0	0
T109	128123	3	0	0