Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10
11CoveredT10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 13110651 13109813 0 0
selKnown1 14792392 14791554 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 13110651 13109813 0 0
T1 1104 1102 0 0
T2 390 388 0 0
T3 3652 3650 0 0
T4 394 392 0 0
T5 7006 7004 0 0
T6 110980 110976 0 0
T7 173830 173826 0 0
T9 19 17 0 0
T10 0 3 0 0
T15 442 438 0 0
T21 2 0 0 0
T25 12 10 0 0
T29 42 40 0 0
T30 0 20 0 0
T32 352 348 0 0
T33 316 312 0 0
T34 0 36 0 0
T55 2 0 0 0
T58 0 4 0 0
T59 0 5 0 0
T110 0 11 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 14792392 14791554 0 0
T1 3584 3582 0 0
T2 1562 1560 0 0
T3 8234 8232 0 0
T4 1184 1182 0 0
T5 10883 10881 0 0
T6 458984 458980 0 0
T7 285057 285053 0 0
T9 10 8 0 0
T10 0 4 0 0
T15 2836 2832 0 0
T21 2 0 0 0
T25 12 10 0 0
T29 42 40 0 0
T30 0 20 0 0
T32 2327 2323 0 0
T33 3304 3300 0 0
T34 0 12 0 0
T55 2 0 0 0
T58 0 8 0 0
T110 0 6 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10
11CoveredT10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2109014 2108910 0 0
selKnown1 3790943 3790839 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2109014 2108910 0 0
T1 552 551 0 0
T2 195 194 0 0
T3 1826 1825 0 0
T4 197 196 0 0
T5 3503 3502 0 0
T6 55486 55485 0 0
T7 86906 86905 0 0
T15 220 219 0 0
T32 175 174 0 0
T33 157 156 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3790943 3790839 0 0
T1 3032 3031 0 0
T2 1367 1366 0 0
T3 6408 6407 0 0
T4 987 986 0 0
T5 7380 7379 0 0
T6 403490 403489 0 0
T7 198139 198138 0 0
T15 2614 2613 0 0
T32 2150 2149 0 0
T33 3145 3144 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10
11CoveredT10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 292 188 0 0
selKnown1 272 168 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 292 188 0 0
T6 4 3 0 0
T7 6 5 0 0
T9 5 4 0 0
T10 0 1 0 0
T15 1 0 0 0
T21 1 0 0 0
T25 6 5 0 0
T29 21 20 0 0
T30 0 10 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 0 18 0 0
T55 1 0 0 0
T58 0 4 0 0
T110 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 272 168 0 0
T6 4 3 0 0
T7 6 5 0 0
T9 5 4 0 0
T10 0 2 0 0
T15 1 0 0 0
T21 1 0 0 0
T25 6 5 0 0
T29 21 20 0 0
T30 0 10 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 0 6 0 0
T55 1 0 0 0
T58 0 4 0 0
T110 0 3 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10
11CoveredT10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10999592 10999277 0 0
selKnown1 10999592 10999277 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10999592 10999277 0 0
T1 552 551 0 0
T2 195 194 0 0
T3 1826 1825 0 0
T4 197 196 0 0
T5 3503 3502 0 0
T6 55486 55485 0 0
T7 86906 86905 0 0
T15 220 219 0 0
T32 175 174 0 0
T33 157 156 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10999592 10999277 0 0
T1 552 551 0 0
T2 195 194 0 0
T3 1826 1825 0 0
T4 197 196 0 0
T5 3503 3502 0 0
T6 55486 55485 0 0
T7 86906 86905 0 0
T15 220 219 0 0
T32 175 174 0 0
T33 157 156 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10
11CoveredT10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1753 1438 0 0
selKnown1 1585 1270 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1753 1438 0 0
T6 4 3 0 0
T7 12 11 0 0
T9 14 13 0 0
T10 0 2 0 0
T15 1 0 0 0
T21 1 0 0 0
T25 6 5 0 0
T29 21 20 0 0
T30 0 10 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 0 18 0 0
T55 1 0 0 0
T59 0 5 0 0
T110 0 8 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1585 1270 0 0
T6 4 3 0 0
T7 6 5 0 0
T9 5 4 0 0
T10 0 2 0 0
T15 1 0 0 0
T21 1 0 0 0
T25 6 5 0 0
T29 21 20 0 0
T30 0 10 0 0
T32 1 0 0 0
T33 1 0 0 0
T34 0 6 0 0
T55 1 0 0 0
T58 0 4 0 0
T110 0 3 0 0

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