SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 624 | 624 | 0 | 0 |
OutputsKnown_A | 22745658 | 22636128 | 0 | 0 |
gen_flops.OutputDelay_A | 11372829 | 11315616 | 0 | 936 |
gen_no_flops.OutputDelay_A | 11372829 | 11318064 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 624 | 624 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T15 | 6 | 6 | 0 | 0 |
T32 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22745658 | 22636128 | 0 | 0 |
T1 | 18192 | 17772 | 0 | 0 |
T2 | 8202 | 7872 | 0 | 0 |
T3 | 38448 | 38142 | 0 | 0 |
T4 | 5922 | 5436 | 0 | 0 |
T5 | 44280 | 43728 | 0 | 0 |
T6 | 2420940 | 2419260 | 0 | 0 |
T7 | 1188834 | 1186614 | 0 | 0 |
T15 | 15684 | 15258 | 0 | 0 |
T32 | 12900 | 12498 | 0 | 0 |
T33 | 18870 | 18534 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11372829 | 11315616 | 0 | 936 |
T1 | 9096 | 8877 | 0 | 9 |
T2 | 4101 | 3927 | 0 | 9 |
T3 | 19224 | 19062 | 0 | 9 |
T4 | 2961 | 2709 | 0 | 9 |
T5 | 22140 | 21855 | 0 | 9 |
T6 | 1210470 | 1209594 | 0 | 9 |
T7 | 594417 | 593253 | 0 | 9 |
T15 | 7842 | 7620 | 0 | 9 |
T32 | 6450 | 6240 | 0 | 9 |
T33 | 9435 | 9258 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11372829 | 11318064 | 0 | 0 |
T1 | 9096 | 8886 | 0 | 0 |
T2 | 4101 | 3936 | 0 | 0 |
T3 | 19224 | 19071 | 0 | 0 |
T4 | 2961 | 2718 | 0 | 0 |
T5 | 22140 | 21864 | 0 | 0 |
T6 | 1210470 | 1209630 | 0 | 0 |
T7 | 594417 | 593307 | 0 | 0 |
T15 | 7842 | 7629 | 0 | 0 |
T32 | 6450 | 6249 | 0 | 0 |
T33 | 9435 | 9267 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 104 | 104 | 0 | 0 |
OutputsKnown_A | 3790943 | 3772688 | 0 | 0 |
gen_flops.OutputDelay_A | 3790943 | 3771872 | 0 | 312 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 104 | 104 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3771872 | 0 | 312 |
T1 | 3032 | 2959 | 0 | 3 |
T2 | 1367 | 1309 | 0 | 3 |
T3 | 6408 | 6354 | 0 | 3 |
T4 | 987 | 903 | 0 | 3 |
T5 | 7380 | 7285 | 0 | 3 |
T6 | 403490 | 403198 | 0 | 3 |
T7 | 198139 | 197751 | 0 | 3 |
T15 | 2614 | 2540 | 0 | 3 |
T32 | 2150 | 2080 | 0 | 3 |
T33 | 3145 | 3086 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 104 | 104 | 0 | 0 |
OutputsKnown_A | 3790943 | 3772688 | 0 | 0 |
gen_flops.OutputDelay_A | 3790943 | 3771872 | 0 | 312 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 104 | 104 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3771872 | 0 | 312 |
T1 | 3032 | 2959 | 0 | 3 |
T2 | 1367 | 1309 | 0 | 3 |
T3 | 6408 | 6354 | 0 | 3 |
T4 | 987 | 903 | 0 | 3 |
T5 | 7380 | 7285 | 0 | 3 |
T6 | 403490 | 403198 | 0 | 3 |
T7 | 198139 | 197751 | 0 | 3 |
T15 | 2614 | 2540 | 0 | 3 |
T32 | 2150 | 2080 | 0 | 3 |
T33 | 3145 | 3086 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 104 | 104 | 0 | 0 |
OutputsKnown_A | 3790943 | 3772688 | 0 | 0 |
gen_no_flops.OutputDelay_A | 3790943 | 3772688 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 104 | 104 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 104 | 104 | 0 | 0 |
OutputsKnown_A | 3790943 | 3772688 | 0 | 0 |
gen_flops.OutputDelay_A | 3790943 | 3771872 | 0 | 312 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 104 | 104 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3771872 | 0 | 312 |
T1 | 3032 | 2959 | 0 | 3 |
T2 | 1367 | 1309 | 0 | 3 |
T3 | 6408 | 6354 | 0 | 3 |
T4 | 987 | 903 | 0 | 3 |
T5 | 7380 | 7285 | 0 | 3 |
T6 | 403490 | 403198 | 0 | 3 |
T7 | 198139 | 197751 | 0 | 3 |
T15 | 2614 | 2540 | 0 | 3 |
T32 | 2150 | 2080 | 0 | 3 |
T33 | 3145 | 3086 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 104 | 104 | 0 | 0 |
OutputsKnown_A | 3790943 | 3772688 | 0 | 0 |
gen_no_flops.OutputDelay_A | 3790943 | 3772688 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 104 | 104 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 104 | 104 | 0 | 0 |
OutputsKnown_A | 3790943 | 3772688 | 0 | 0 |
gen_no_flops.OutputDelay_A | 3790943 | 3772688 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 104 | 104 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3790943 | 3772688 | 0 | 0 |
T1 | 3032 | 2962 | 0 | 0 |
T2 | 1367 | 1312 | 0 | 0 |
T3 | 6408 | 6357 | 0 | 0 |
T4 | 987 | 906 | 0 | 0 |
T5 | 7380 | 7288 | 0 | 0 |
T6 | 403490 | 403210 | 0 | 0 |
T7 | 198139 | 197769 | 0 | 0 |
T15 | 2614 | 2543 | 0 | 0 |
T32 | 2150 | 2083 | 0 | 0 |
T33 | 3145 | 3089 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |