Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 178128 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 537064 1 T2 9 T4 4 T5 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 434166 1 T2 10 T4 8 T16 8
values[0x0] 138210 1 T5 11 T16 1 T11 2
values[0x1] 142816 1 T2 1 T4 1 T5 15



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 137131 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 578061 1 T2 9 T4 6 T5 11



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2601 1 T47 4 T48 4 T45 17
valid_sources[0x01] 2535 1 T47 2 T44 12 T45 23
valid_sources[0x02] 2858 1 T21 1 T47 5 T48 5
valid_sources[0x03] 2510 1 T15 2 T44 5 T48 3
valid_sources[0x04] 2601 1 T47 2 T44 17 T48 2
valid_sources[0x05] 2565 1 T13 65 T44 8 T48 5
valid_sources[0x06] 2984 1 T44 3 T48 4 T45 23
valid_sources[0x07] 2522 1 T47 4 T44 3 T48 7
valid_sources[0x08] 2758 1 T2 3 T25 8 T47 5
valid_sources[0x09] 2499 1 T2 5 T47 1 T44 10
valid_sources[0x0a] 2644 1 T47 4 T44 30 T48 3
valid_sources[0x0b] 2554 1 T47 3 T48 5 T45 12
valid_sources[0x0c] 2575 1 T14 2 T47 3 T44 4
valid_sources[0x0d] 3071 1 T9 9 T44 1 T48 3
valid_sources[0x0e] 3095 1 T15 1 T8 2 T47 6
valid_sources[0x0f] 2948 1 T21 2 T47 2 T44 20
valid_sources[0x10] 2820 1 T47 2 T44 2 T48 7
valid_sources[0x11] 2613 1 T27 3 T47 8 T44 3
valid_sources[0x12] 3099 1 T47 4 T44 1 T48 1
valid_sources[0x13] 2593 1 T47 3 T44 3 T48 2
valid_sources[0x14] 2857 1 T47 2 T44 4 T48 6
valid_sources[0x15] 2533 1 T47 1 T44 2 T48 2
valid_sources[0x16] 3602 1 T15 1 T47 3 T44 1
valid_sources[0x17] 2752 1 T15 3 T47 5 T44 6
valid_sources[0x18] 5200 1 T47 3 T48 7 T45 18
valid_sources[0x19] 2943 1 T47 5 T44 9 T48 7
valid_sources[0x1a] 2415 1 T47 1 T48 4 T45 14
valid_sources[0x1b] 2539 1 T15 2 T47 2 T44 3
valid_sources[0x1c] 2816 1 T18 1 T23 8 T47 4
valid_sources[0x1d] 2265 1 T47 4 T48 1 T45 21
valid_sources[0x1e] 2591 1 T15 1 T47 8 T44 1
valid_sources[0x1f] 14032 1 T5 1 T47 2 T44 10
valid_sources[0x20] 2676 1 T14 2 T47 7 T44 5
valid_sources[0x21] 2471 1 T16 2 T47 1 T44 6
valid_sources[0x22] 2971 1 T47 1 T44 19 T48 2
valid_sources[0x23] 2538 1 T47 2 T44 1 T48 4
valid_sources[0x24] 2390 1 T11 1 T47 4 T48 9
valid_sources[0x25] 2636 1 T44 2 T48 6 T45 22
valid_sources[0x26] 3315 1 T20 4 T44 10 T48 6
valid_sources[0x27] 2622 1 T47 1 T48 11 T45 30
valid_sources[0x28] 2649 1 T47 4 T44 4 T48 3
valid_sources[0x29] 2902 1 T47 2 T48 4 T45 22
valid_sources[0x2a] 2527 1 T11 2 T47 6 T44 4
valid_sources[0x2b] 2694 1 T44 1 T48 6 T45 29
valid_sources[0x2c] 2591 1 T8 1 T47 4 T44 12
valid_sources[0x2d] 2832 1 T14 3 T135 1 T15 1
valid_sources[0x2e] 2711 1 T47 2 T44 6 T48 2
valid_sources[0x2f] 2983 1 T15 2 T47 13 T44 15
valid_sources[0x30] 2503 1 T48 6 T45 29 T64 3
valid_sources[0x31] 2786 1 T52 1 T47 5 T44 4
valid_sources[0x32] 2743 1 T47 3 T44 2 T48 5
valid_sources[0x33] 2629 1 T17 1 T47 6 T48 1
valid_sources[0x34] 2860 1 T44 11 T48 3 T45 25
valid_sources[0x35] 2843 1 T47 5 T44 9 T48 5
valid_sources[0x36] 2594 1 T27 1 T44 5 T48 6
valid_sources[0x37] 3001 1 T47 5 T44 7 T48 9
valid_sources[0x38] 2398 1 T4 9 T5 1 T27 3
valid_sources[0x39] 2986 1 T15 6 T9 4 T47 4
valid_sources[0x3a] 3045 1 T52 1 T27 1 T47 1
valid_sources[0x3b] 2875 1 T47 4 T44 8 T48 3
valid_sources[0x3c] 2553 1 T47 2 T44 2 T48 6
valid_sources[0x3d] 2557 1 T47 2 T48 2 T45 24
valid_sources[0x3e] 2944 1 T17 1 T9 9 T47 2
valid_sources[0x3f] 2934 1 T47 3 T44 5 T48 8
valid_sources[0x40] 2603 1 T52 1 T17 1 T15 1
valid_sources[0x41] 2830 1 T47 3 T44 4 T48 2
valid_sources[0x42] 2455 1 T15 8 T47 5 T44 4
valid_sources[0x43] 2803 1 T52 1 T12 13 T47 1
valid_sources[0x44] 2562 1 T5 1 T27 2 T47 1
valid_sources[0x45] 2701 1 T15 3 T8 1 T27 2
valid_sources[0x46] 2645 1 T14 2 T8 1 T47 6
valid_sources[0x47] 2925 1 T5 1 T47 1 T44 2
valid_sources[0x48] 2790 1 T47 1 T44 4 T48 5
valid_sources[0x49] 2747 1 T8 1 T47 1 T44 16
valid_sources[0x4a] 2667 1 T5 2 T15 1 T47 5
valid_sources[0x4b] 2426 1 T8 2 T47 3 T44 9
valid_sources[0x4c] 2634 1 T47 3 T48 8 T45 20
valid_sources[0x4d] 2624 1 T48 6 T45 19 T64 9
valid_sources[0x4e] 2680 1 T47 6 T44 7 T48 6
valid_sources[0x4f] 2686 1 T47 1 T44 3 T48 3
valid_sources[0x50] 2933 1 T47 4 T44 1 T48 7
valid_sources[0x51] 2379 1 T15 1 T44 6 T48 6
valid_sources[0x52] 2489 1 T8 1 T44 26 T48 6
valid_sources[0x53] 2833 1 T8 1 T47 3 T44 4
valid_sources[0x54] 2824 1 T17 1 T47 6 T44 11
valid_sources[0x55] 2645 1 T47 1 T44 3 T48 4
valid_sources[0x56] 2691 1 T47 3 T44 2 T48 7
valid_sources[0x57] 2615 1 T47 3 T44 1 T48 2
valid_sources[0x58] 2547 1 T47 2 T44 22 T48 8
valid_sources[0x59] 2752 1 T135 1 T8 1 T47 3
valid_sources[0x5a] 2565 1 T15 1 T47 2 T44 13
valid_sources[0x5b] 2697 1 T9 4 T47 2 T48 2
valid_sources[0x5c] 2808 1 T14 2 T47 1 T44 5
valid_sources[0x5d] 2807 1 T47 4 T44 3 T48 5
valid_sources[0x5e] 4190 1 T47 4 T44 3 T48 3
valid_sources[0x5f] 3413 1 T47 2 T44 25 T48 3
valid_sources[0x60] 2621 1 T5 1 T15 1 T47 3
valid_sources[0x61] 2597 1 T47 4 T44 4 T48 5
valid_sources[0x62] 2359 1 T17 1 T15 1 T47 2
valid_sources[0x63] 2546 1 T16 1 T9 7 T47 3
valid_sources[0x64] 2496 1 T47 1 T44 8 T48 4
valid_sources[0x65] 2496 1 T5 1 T52 1 T47 1
valid_sources[0x66] 2531 1 T48 5 T45 26 T76 2
valid_sources[0x67] 2458 1 T47 2 T44 14 T48 2
valid_sources[0x68] 2620 1 T47 2 T44 5 T48 4
valid_sources[0x69] 2616 1 T47 1 T44 8 T48 5
valid_sources[0x6a] 2714 1 T17 1 T44 7 T48 3
valid_sources[0x6b] 2679 1 T15 2 T47 1 T44 4
valid_sources[0x6c] 3171 1 T47 1 T45 32 T64 1
valid_sources[0x6d] 2607 1 T47 5 T44 3 T48 2
valid_sources[0x6e] 2537 1 T27 5 T48 3 T45 12
valid_sources[0x6f] 2929 1 T44 3 T48 7 T45 19
valid_sources[0x70] 2662 1 T5 1 T47 5 T44 8
valid_sources[0x71] 2499 1 T47 1 T48 5 T45 19
valid_sources[0x72] 2697 1 T8 2 T47 2 T44 2
valid_sources[0x73] 2732 1 T47 3 T48 3 T45 31
valid_sources[0x74] 2548 1 T5 1 T17 2 T15 1
valid_sources[0x75] 2879 1 T2 1 T47 3 T44 14
valid_sources[0x76] 2676 1 T135 1 T47 6 T44 2
valid_sources[0x77] 2720 1 T47 2 T44 1 T48 1
valid_sources[0x78] 2712 1 T52 2 T8 2 T47 1
valid_sources[0x79] 2567 1 T14 3 T48 6 T45 13
valid_sources[0x7a] 2538 1 T17 1 T15 5 T47 1
valid_sources[0x7b] 2622 1 T47 6 T44 4 T48 10
valid_sources[0x7c] 2281 1 T5 1 T47 2 T48 6
valid_sources[0x7d] 2518 1 T52 1 T47 2 T44 14
valid_sources[0x7e] 2563 1 T47 1 T44 2 T48 4
valid_sources[0x7f] 2789 1 T47 5 T44 3 T48 6
valid_sources[0x80] 2630 1 T9 4 T47 2 T44 15



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 263995 1 T2 9 T4 4 T16 4
values[0x0] all_enables biggest_size 136595 1 T5 5 T10 1 T17 1
values[0x1] all_enables biggest_size 136474 1 T5 3 T11 2 T52 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4365 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 17822 1 T36 1 T37 1 T38 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8221 1 T47 108 T44 38 T48 6
values[0x0] 6824 1 T36 9 T37 1 T38 4
values[0x1] 7142 1 T36 5 T37 2 T38 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3294 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 18893 1 T36 4 T37 1 T38 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 67 1 T136 1 T64 1 T85 2
valid_sources[0x01] 83 1 T43 1 T71 1 T64 1
valid_sources[0x02] 74 1 T137 1 T72 2 T73 3
valid_sources[0x03] 58 1 T138 2 T81 1 T60 2
valid_sources[0x04] 114 1 T139 1 T47 3 T74 3
valid_sources[0x05] 137 1 T140 1 T47 1 T64 1
valid_sources[0x06] 113 1 T137 1 T47 2 T64 2
valid_sources[0x07] 60 1 T36 1 T47 2 T85 1
valid_sources[0x08] 73 1 T50 2 T51 1 T64 1
valid_sources[0x09] 153 1 T45 2 T64 1 T46 1
valid_sources[0x0a] 73 1 T139 1 T47 3 T45 1
valid_sources[0x0b] 38 1 T64 2 T73 3 T86 3
valid_sources[0x0c] 59 1 T141 3 T72 1 T86 6
valid_sources[0x0d] 64 1 T40 1 T64 1 T86 1
valid_sources[0x0e] 48 1 T64 1 T65 1 T84 1
valid_sources[0x0f] 143 1 T81 3 T83 1 T84 1
valid_sources[0x10] 61 1 T142 1 T47 4 T85 1
valid_sources[0x11] 80 1 T143 1 T60 1 T144 2
valid_sources[0x12] 58 1 T47 9 T64 2 T72 1
valid_sources[0x13] 84 1 T71 1 T145 1 T146 1
valid_sources[0x14] 39 1 T86 1 T114 1 T147 2
valid_sources[0x15] 100 1 T51 3 T67 1 T142 2
valid_sources[0x16] 40 1 T64 1 T60 4 T144 3
valid_sources[0x17] 54 1 T36 1 T145 1 T64 2
valid_sources[0x18] 83 1 T141 1 T47 1 T46 1
valid_sources[0x19] 80 1 T137 1 T47 1 T59 8
valid_sources[0x1a] 92 1 T148 16 T64 2 T72 2
valid_sources[0x1b] 53 1 T49 1 T84 2 T60 1
valid_sources[0x1c] 71 1 T47 5 T45 1 T64 1
valid_sources[0x1d] 438 1 T36 1 T72 1 T60 3
valid_sources[0x1e] 39 1 T64 1 T72 1 T60 5
valid_sources[0x1f] 110 1 T140 1 T47 2 T72 1
valid_sources[0x20] 72 1 T47 2 T64 2 T65 1
valid_sources[0x21] 95 1 T149 7 T47 4 T64 1
valid_sources[0x22] 138 1 T64 1 T72 3 T74 3
valid_sources[0x23] 50 1 T46 1 T84 1 T86 1
valid_sources[0x24] 110 1 T44 42 T45 1 T64 1
valid_sources[0x25] 44 1 T140 1 T73 3 T60 6
valid_sources[0x26] 85 1 T136 1 T47 4 T46 1
valid_sources[0x27] 108 1 T145 1 T142 1 T150 4
valid_sources[0x28] 74 1 T43 1 T59 4 T144 1
valid_sources[0x29] 52 1 T138 1 T47 1 T64 1
valid_sources[0x2a] 53 1 T49 1 T151 4 T72 2
valid_sources[0x2b] 79 1 T75 1 T60 6 T86 4
valid_sources[0x2c] 72 1 T40 1 T85 3 T60 1
valid_sources[0x2d] 54 1 T86 1 T144 1 T147 2
valid_sources[0x2e] 75 1 T47 1 T64 2 T85 2
valid_sources[0x2f] 93 1 T65 4 T86 1 T144 3
valid_sources[0x30] 228 1 T43 1 T72 1 T65 2
valid_sources[0x31] 86 1 T47 1 T76 8 T72 1
valid_sources[0x32] 175 1 T51 1 T72 2 T81 1
valid_sources[0x33] 57 1 T140 1 T64 2 T46 1
valid_sources[0x34] 64 1 T49 1 T143 2 T47 1
valid_sources[0x35] 76 1 T46 1 T60 4 T111 2
valid_sources[0x36] 78 1 T142 2 T81 1 T82 2
valid_sources[0x37] 73 1 T152 7 T60 1 T86 6
valid_sources[0x38] 59 1 T146 1 T47 4 T45 1
valid_sources[0x39] 104 1 T141 1 T45 1 T64 1
valid_sources[0x3a] 83 1 T139 1 T47 2 T64 1
valid_sources[0x3b] 78 1 T47 9 T72 4 T59 6
valid_sources[0x3c] 54 1 T38 1 T64 1 T83 1
valid_sources[0x3d] 72 1 T36 1 T153 3 T154 3
valid_sources[0x3e] 99 1 T43 1 T51 1 T54 1
valid_sources[0x3f] 81 1 T40 1 T136 2 T153 3
valid_sources[0x40] 92 1 T64 1 T46 1 T72 1
valid_sources[0x41] 65 1 T47 4 T45 2 T72 1
valid_sources[0x42] 72 1 T145 1 T45 3 T72 1
valid_sources[0x43] 45 1 T142 2 T72 1 T60 13
valid_sources[0x44] 239 1 T47 7 T64 1 T72 1
valid_sources[0x45] 149 1 T136 1 T142 1 T141 1
valid_sources[0x46] 77 1 T140 1 T64 2 T46 1
valid_sources[0x47] 101 1 T71 1 T153 2 T47 4
valid_sources[0x48] 67 1 T40 1 T71 1 T139 1
valid_sources[0x49] 60 1 T45 1 T65 2 T83 1
valid_sources[0x4a] 132 1 T43 1 T145 1 T64 5
valid_sources[0x4b] 52 1 T38 1 T47 1 T73 3
valid_sources[0x4c] 67 1 T64 1 T72 1 T81 1
valid_sources[0x4d] 72 1 T43 1 T139 2 T47 2
valid_sources[0x4e] 74 1 T47 7 T64 1 T46 1
valid_sources[0x4f] 43 1 T136 1 T72 1 T81 1
valid_sources[0x50] 314 1 T43 1 T54 1 T47 6
valid_sources[0x51] 78 1 T40 1 T140 1 T72 2
valid_sources[0x52] 126 1 T72 1 T81 1 T60 4
valid_sources[0x53] 54 1 T47 3 T45 2 T86 1
valid_sources[0x54] 86 1 T41 4 T45 3 T72 1
valid_sources[0x55] 45 1 T60 3 T86 6 T90 3
valid_sources[0x56] 92 1 T47 1 T64 2 T59 6
valid_sources[0x57] 115 1 T42 1 T138 1 T47 4
valid_sources[0x58] 58 1 T141 1 T64 1 T46 1
valid_sources[0x59] 69 1 T49 2 T47 6 T46 2
valid_sources[0x5a] 88 1 T45 5 T60 1 T144 7
valid_sources[0x5b] 111 1 T46 2 T60 1 T86 4
valid_sources[0x5c] 94 1 T47 1 T64 1 T65 3
valid_sources[0x5d] 59 1 T145 1 T47 6 T81 1
valid_sources[0x5e] 114 1 T36 1 T145 1 T64 3
valid_sources[0x5f] 72 1 T46 1 T60 2 T86 5
valid_sources[0x60] 160 1 T138 1 T72 1 T74 7
valid_sources[0x61] 99 1 T155 17 T44 1 T64 1
valid_sources[0x62] 101 1 T47 1 T83 1 T60 4
valid_sources[0x63] 71 1 T145 2 T143 2 T137 2
valid_sources[0x64] 70 1 T54 5 T139 2 T47 6
valid_sources[0x65] 50 1 T49 1 T46 2 T86 3
valid_sources[0x66] 94 1 T36 1 T47 3 T64 1
valid_sources[0x67] 50 1 T38 1 T71 1 T139 1
valid_sources[0x68] 62 1 T64 1 T72 2 T65 1
valid_sources[0x69] 84 1 T156 11 T47 1 T44 1
valid_sources[0x6a] 72 1 T64 1 T74 6 T83 2
valid_sources[0x6b] 56 1 T50 1 T71 1 T47 1
valid_sources[0x6c] 85 1 T140 1 T47 5 T64 2
valid_sources[0x6d] 68 1 T138 2 T45 1 T64 2
valid_sources[0x6e] 80 1 T66 3 T141 2 T47 3
valid_sources[0x6f] 84 1 T64 2 T80 2 T60 5
valid_sources[0x70] 74 1 T72 1 T86 1 T144 3
valid_sources[0x71] 210 1 T40 1 T47 1 T64 1
valid_sources[0x72] 830 1 T157 13 T47 2 T64 2
valid_sources[0x73] 49 1 T38 1 T139 1 T47 4
valid_sources[0x74] 53 1 T50 1 T136 1 T72 2
valid_sources[0x75] 87 1 T83 1 T84 1 T60 2
valid_sources[0x76] 92 1 T158 14 T143 1 T72 2
valid_sources[0x77] 141 1 T141 1 T47 2 T72 1
valid_sources[0x78] 70 1 T51 1 T139 1 T72 1
valid_sources[0x79] 75 1 T36 1 T45 2 T64 1
valid_sources[0x7a] 75 1 T47 1 T46 1 T72 1
valid_sources[0x7b] 44 1 T47 1 T84 1 T60 1
valid_sources[0x7c] 137 1 T47 3 T45 2 T46 1
valid_sources[0x7d] 140 1 T70 10 T45 1 T64 2
valid_sources[0x7e] 86 1 T136 1 T60 11 T86 3
valid_sources[0x7f] 56 1 T47 6 T64 1 T72 3
valid_sources[0x80] 98 1 T64 1 T65 11 T83 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 5808 1 T47 104 T44 32 T48 3
values[0x0] all_enables biggest_size 6098 1 T36 1 T38 2 T43 2
values[0x1] all_enables biggest_size 5916 1 T37 1 T38 1 T43 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%