SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 736444 | 1 | T2 | 11 | T4 | 9 | T5 | 26 | |||
auto[1] | 17128 | 1 | T14 | 80 | T15 | 80 | T47 | 560 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 753379 | 1 | T2 | 11 | T4 | 9 | T5 | 26 | |||
values[1] | 20 | 1 | T45 | 1 | T46 | 1 | T73 | 2 | |||
values[2] | 4 | 1 | T45 | 1 | T122 | 1 | T123 | 1 | |||
values[3] | 109 | 1 | T45 | 2 | T46 | 6 | T73 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 753381 | 1 | T2 | 11 | T4 | 9 | T5 | 26 | |||
values[1] | 20 | 1 | T46 | 2 | T73 | 1 | T85 | 1 | |||
values[2] | 4 | 1 | T124 | 1 | T122 | 1 | T125 | 1 | |||
values[3] | 97 | 1 | T45 | 2 | T46 | 2 | T73 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 753282 | 1 | T2 | 11 | T4 | 9 | T5 | 26 | |||
auto[TlIntgErrCmd] | 99 | 1 | T45 | 2 | T46 | 6 | T73 | 2 | |||
auto[TlIntgErrData] | 97 | 1 | T45 | 6 | T46 | 1 | T73 | 5 | |||
auto[TlIntgErrBoth] | 94 | 1 | T45 | 2 | T46 | 3 | T73 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 36935 | 0 | T36 | 14 | T37 | 3 | T38 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36745 | 1 | T36 | 14 | T37 | 3 | T38 | 9 | |||
values[1] | 28 | 1 | T45 | 1 | T74 | 1 | T126 | 2 | |||
values[2] | 4 | 1 | T127 | 1 | T128 | 1 | T129 | 2 | |||
values[3] | 95 | 1 | T45 | 2 | T46 | 5 | T73 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36729 | 1 | T36 | 14 | T37 | 3 | T38 | 9 | |||
values[1] | 29 | 1 | T45 | 2 | T73 | 2 | T85 | 1 | |||
values[2] | 7 | 1 | T85 | 1 | T130 | 1 | T124 | 1 | |||
values[3] | 105 | 1 | T45 | 1 | T46 | 3 | T73 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 36645 | 1 | T36 | 14 | T37 | 3 | T38 | 9 | |||
auto[TlIntgErrCmd] | 84 | 1 | T45 | 4 | T46 | 3 | T73 | 2 | |||
auto[TlIntgErrData] | 100 | 1 | T45 | 4 | T46 | 4 | T73 | 3 | |||
auto[TlIntgErrBoth] | 106 | 1 | T45 | 2 | T46 | 3 | T73 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |