Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
214987 |
1 |
|
T2 |
2 |
|
T4 |
5 |
|
T5 |
18 |
full_word |
538585 |
1 |
|
T2 |
9 |
|
T4 |
4 |
|
T5 |
8 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
753282 |
1 |
|
T2 |
11 |
|
T4 |
9 |
|
T5 |
26 |
auto[TlIntgErrCmd] |
99 |
1 |
|
T45 |
2 |
|
T46 |
6 |
|
T73 |
2 |
auto[TlIntgErrData] |
97 |
1 |
|
T45 |
6 |
|
T46 |
1 |
|
T73 |
5 |
auto[TlIntgErrBoth] |
94 |
1 |
|
T45 |
2 |
|
T46 |
3 |
|
T73 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
435898 |
1 |
|
T2 |
10 |
|
T4 |
8 |
|
T16 |
8 |
auto[1] |
317674 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
26 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
171614 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T16 |
4 |
auto[TlIntgErrNone] |
partial |
auto[1] |
43109 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
18 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
264158 |
1 |
|
T2 |
9 |
|
T4 |
4 |
|
T16 |
4 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
274401 |
1 |
|
T5 |
8 |
|
T11 |
2 |
|
T10 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
36 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T73 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
55 |
1 |
|
T45 |
1 |
|
T46 |
4 |
|
T73 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
4 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T132 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T124 |
1 |
|
T133 |
1 |
|
T122 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
43 |
1 |
|
T45 |
5 |
|
T46 |
1 |
|
T85 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
43 |
1 |
|
T45 |
1 |
|
T73 |
4 |
|
T74 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
7 |
1 |
|
T73 |
1 |
|
T85 |
1 |
|
T124 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
4 |
1 |
|
T126 |
1 |
|
T127 |
2 |
|
T133 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
33 |
1 |
|
T45 |
1 |
|
T46 |
1 |
|
T73 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
54 |
1 |
|
T45 |
1 |
|
T46 |
2 |
|
T73 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
T126 |
1 |
|
T124 |
1 |
|
T129 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
4 |
1 |
|
T130 |
1 |
|
T125 |
1 |
|
T134 |
1 |