Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.35	87.88	61.70	87.54		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	28841299	11867	0	0
late_debug_enable_rd_A	28841299	2916	0	0
late_debug_enable_regwen_rd_A	28841299	1686	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28841299	11867	0	0
T44	90774	22	0	0
T45	15817	4	0	0
T46	22836	2	0	0
T47	8432	543	0	0
T59	415389	43	0	0
T64	14336	243	0	0
T65	38260	281	0	0
T72	33177	50	0	0
T73	48194	2	0	0
T85	24148	3	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28841299	2916	0	0
T59	415389	38	0	0
T74	54176	22	0	0
T75	60572	4	0	0
T76	8015	5	0	0
T77	7948	3	0	0
T79	6026	1	0	0
T90	25870	32	0	0
T111	379370	1028	0	0
T114	47520	9	0	0
T115	8114	16	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28841299	1686	0	0
T59	415389	51	0	0
T74	54176	34	0	0
T76	8015	4	0	0
T77	7948	10	0	0
T90	25870	31	0	0
T114	47520	11	0	0
T115	8114	14	0	0
T116	126075	97	0	0
T117	16730	96	0	0
T118	490171	430	0	0