Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
12256313 |
12255513 |
0 |
0 |
selKnown1 |
11688616 |
11687816 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12256313 |
12255513 |
0 |
0 |
T1 |
7056 |
7052 |
0 |
0 |
T2 |
1430 |
1426 |
0 |
0 |
T3 |
49817 |
49813 |
0 |
0 |
T4 |
2934 |
2930 |
0 |
0 |
T5 |
49292 |
49288 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T26 |
4164 |
4160 |
0 |
0 |
T29 |
0 |
18 |
0 |
0 |
T30 |
0 |
134 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T33 |
0 |
12 |
0 |
0 |
T34 |
0 |
40 |
0 |
0 |
T35 |
0 |
40 |
0 |
0 |
T36 |
316 |
312 |
0 |
0 |
T37 |
312 |
308 |
0 |
0 |
T38 |
422 |
418 |
0 |
0 |
T43 |
370 |
366 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11688616 |
11687816 |
0 |
0 |
T1 |
25957 |
25953 |
0 |
0 |
T2 |
2578 |
2574 |
0 |
0 |
T3 |
100700 |
100696 |
0 |
0 |
T4 |
5633 |
5629 |
0 |
0 |
T5 |
125620 |
125616 |
0 |
0 |
T13 |
0 |
10 |
0 |
0 |
T26 |
6876 |
6872 |
0 |
0 |
T29 |
0 |
18 |
0 |
0 |
T30 |
0 |
134 |
0 |
0 |
T34 |
0 |
40 |
0 |
0 |
T35 |
0 |
40 |
0 |
0 |
T36 |
2174 |
2170 |
0 |
0 |
T37 |
1432 |
1428 |
0 |
0 |
T38 |
1259 |
1255 |
0 |
0 |
T43 |
1492 |
1488 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2232785 |
2232688 |
0 |
0 |
selKnown1 |
1665186 |
1665089 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2232785 |
2232688 |
0 |
0 |
T1 |
3507 |
3506 |
0 |
0 |
T2 |
714 |
713 |
0 |
0 |
T3 |
24903 |
24902 |
0 |
0 |
T4 |
1466 |
1465 |
0 |
0 |
T5 |
24645 |
24644 |
0 |
0 |
T26 |
2081 |
2080 |
0 |
0 |
T36 |
157 |
156 |
0 |
0 |
T37 |
155 |
154 |
0 |
0 |
T38 |
210 |
209 |
0 |
0 |
T43 |
184 |
183 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1665186 |
1665089 |
0 |
0 |
T1 |
22408 |
22407 |
0 |
0 |
T2 |
1862 |
1861 |
0 |
0 |
T3 |
75787 |
75786 |
0 |
0 |
T4 |
4165 |
4164 |
0 |
0 |
T5 |
100973 |
100972 |
0 |
0 |
T26 |
4793 |
4792 |
0 |
0 |
T36 |
2015 |
2014 |
0 |
0 |
T37 |
1275 |
1274 |
0 |
0 |
T38 |
1047 |
1046 |
0 |
0 |
T43 |
1306 |
1305 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
268 |
171 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T13 |
0 |
5 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T30 |
0 |
67 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
165 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T13 |
0 |
5 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T30 |
0 |
67 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10021758 |
10021455 |
0 |
0 |
selKnown1 |
10021758 |
10021455 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10021758 |
10021455 |
0 |
0 |
T1 |
3507 |
3506 |
0 |
0 |
T2 |
714 |
713 |
0 |
0 |
T3 |
24903 |
24902 |
0 |
0 |
T4 |
1466 |
1465 |
0 |
0 |
T5 |
24645 |
24644 |
0 |
0 |
T26 |
2081 |
2080 |
0 |
0 |
T36 |
157 |
156 |
0 |
0 |
T37 |
155 |
154 |
0 |
0 |
T38 |
210 |
209 |
0 |
0 |
T43 |
184 |
183 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10021758 |
10021455 |
0 |
0 |
T1 |
3507 |
3506 |
0 |
0 |
T2 |
714 |
713 |
0 |
0 |
T3 |
24903 |
24902 |
0 |
0 |
T4 |
1466 |
1465 |
0 |
0 |
T5 |
24645 |
24644 |
0 |
0 |
T26 |
2081 |
2080 |
0 |
0 |
T36 |
157 |
156 |
0 |
0 |
T37 |
155 |
154 |
0 |
0 |
T38 |
210 |
209 |
0 |
0 |
T43 |
184 |
183 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1502 |
1199 |
0 |
0 |
selKnown1 |
1410 |
1107 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1502 |
1199 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T13 |
0 |
5 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T30 |
0 |
67 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1410 |
1107 |
0 |
0 |
T1 |
21 |
20 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T13 |
0 |
5 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T30 |
0 |
67 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T35 |
0 |
20 |
0 |
0 |
T36 |
1 |
0 |
0 |
0 |
T37 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T43 |
1 |
0 |
0 |
0 |
T44 |
0 |
2 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |