SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.35 | 87.88 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 582 | 582 | 0 | 0 |
OutputsKnown_A | 9991116 | 9885624 | 0 | 0 |
gen_flops.OutputDelay_A | 4995558 | 4940454 | 0 | 873 |
gen_no_flops.OutputDelay_A | 4995558 | 4942812 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 582 | 582 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T26 | 6 | 6 | 0 | 0 |
T36 | 6 | 6 | 0 | 0 |
T37 | 6 | 6 | 0 | 0 |
T38 | 6 | 6 | 0 | 0 |
T43 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 9991116 | 9885624 | 0 | 0 |
T1 | 134448 | 126330 | 0 | 0 |
T2 | 11172 | 10758 | 0 | 0 |
T3 | 454722 | 452754 | 0 | 0 |
T4 | 24990 | 24522 | 0 | 0 |
T5 | 605838 | 605370 | 0 | 0 |
T26 | 28758 | 28422 | 0 | 0 |
T36 | 12090 | 11766 | 0 | 0 |
T37 | 7650 | 7260 | 0 | 0 |
T38 | 6282 | 5832 | 0 | 0 |
T43 | 7836 | 7440 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 4995558 | 4940454 | 0 | 873 |
T1 | 67224 | 62976 | 0 | 9 |
T2 | 5586 | 5370 | 0 | 9 |
T3 | 227361 | 226332 | 0 | 9 |
T4 | 12495 | 12252 | 0 | 9 |
T5 | 302919 | 302676 | 0 | 9 |
T26 | 14379 | 14202 | 0 | 9 |
T36 | 6045 | 5874 | 0 | 9 |
T37 | 3825 | 3621 | 0 | 9 |
T38 | 3141 | 2907 | 0 | 9 |
T43 | 3918 | 3711 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 4995558 | 4942812 | 0 | 0 |
T1 | 67224 | 63165 | 0 | 0 |
T2 | 5586 | 5379 | 0 | 0 |
T3 | 227361 | 226377 | 0 | 0 |
T4 | 12495 | 12261 | 0 | 0 |
T5 | 302919 | 302685 | 0 | 0 |
T26 | 14379 | 14211 | 0 | 0 |
T36 | 6045 | 5883 | 0 | 0 |
T37 | 3825 | 3630 | 0 | 0 |
T38 | 3141 | 2916 | 0 | 0 |
T43 | 3918 | 3720 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1665186 | 1647604 | 0 | 0 |
gen_flops.OutputDelay_A | 1665186 | 1646818 | 0 | 291 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T43 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1646818 | 0 | 291 |
T1 | 22408 | 20992 | 0 | 3 |
T2 | 1862 | 1790 | 0 | 3 |
T3 | 75787 | 75444 | 0 | 3 |
T4 | 4165 | 4084 | 0 | 3 |
T5 | 100973 | 100892 | 0 | 3 |
T26 | 4793 | 4734 | 0 | 3 |
T36 | 2015 | 1958 | 0 | 3 |
T37 | 1275 | 1207 | 0 | 3 |
T38 | 1047 | 969 | 0 | 3 |
T43 | 1306 | 1237 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1665186 | 1647604 | 0 | 0 |
gen_flops.OutputDelay_A | 1665186 | 1646818 | 0 | 291 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T43 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1646818 | 0 | 291 |
T1 | 22408 | 20992 | 0 | 3 |
T2 | 1862 | 1790 | 0 | 3 |
T3 | 75787 | 75444 | 0 | 3 |
T4 | 4165 | 4084 | 0 | 3 |
T5 | 100973 | 100892 | 0 | 3 |
T26 | 4793 | 4734 | 0 | 3 |
T36 | 2015 | 1958 | 0 | 3 |
T37 | 1275 | 1207 | 0 | 3 |
T38 | 1047 | 969 | 0 | 3 |
T43 | 1306 | 1237 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1665186 | 1647604 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1665186 | 1647604 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T43 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1665186 | 1647604 | 0 | 0 |
gen_flops.OutputDelay_A | 1665186 | 1646818 | 0 | 291 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T43 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1646818 | 0 | 291 |
T1 | 22408 | 20992 | 0 | 3 |
T2 | 1862 | 1790 | 0 | 3 |
T3 | 75787 | 75444 | 0 | 3 |
T4 | 4165 | 4084 | 0 | 3 |
T5 | 100973 | 100892 | 0 | 3 |
T26 | 4793 | 4734 | 0 | 3 |
T36 | 2015 | 1958 | 0 | 3 |
T37 | 1275 | 1207 | 0 | 3 |
T38 | 1047 | 969 | 0 | 3 |
T43 | 1306 | 1237 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1665186 | 1647604 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1665186 | 1647604 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T43 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1665186 | 1647604 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1665186 | 1647604 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T43 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1665186 | 1647604 | 0 | 0 |
T1 | 22408 | 21055 | 0 | 0 |
T2 | 1862 | 1793 | 0 | 0 |
T3 | 75787 | 75459 | 0 | 0 |
T4 | 4165 | 4087 | 0 | 0 |
T5 | 100973 | 100895 | 0 | 0 |
T26 | 4793 | 4737 | 0 | 0 |
T36 | 2015 | 1961 | 0 | 0 |
T37 | 1275 | 1210 | 0 | 0 |
T38 | 1047 | 972 | 0 | 0 |
T43 | 1306 | 1240 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |