Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.77 60.77


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.77 60.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_rsp_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[56:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 158 60.77
Total Bits 0->1 130 79 60.77
Total Bits 1->0 130 79 60.77

Ports 4 3 75.00
Port Bits 260 158 60.77
Port Bits 0->1 130 79 60.77
Port Bits 1->0 130 79 60.77

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[5:0] Yes Yes *T1,*T3,*T51 Yes T1,T3,T29 INPUT
data_i[56:6] No No No INPUT
data_i[63:57] Yes Yes T1,T3,T28 Yes T1,T3,T50 INPUT
data_o[56:0] Yes Yes T1,T51,T22 Yes T1,T29,T30 OUTPUT
syndrome_o[6:0] Yes Yes T1,T3,T29 Yes T1,T3,T50 OUTPUT
err_o[1:0] Yes Yes T1,T3,T29 Yes T1,T3,T36 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T40,*T41,*T42 Yes T3,T40,T41 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T3,T36,T37 Yes T3,T36,T37 INPUT
data_o[56:0] Yes Yes T40,T41,T42 Yes T3,T40,T41 OUTPUT
syndrome_o[6:0] Yes Yes T3,T40,T41 Yes T3,T40,T41 OUTPUT
err_o[1:0] Yes Yes T3,T40,T41 Yes T3,T40,T41 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T2,*T4,*T16 Yes T2,T36,T4 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T2,T4,T5 Yes T2,T36,T4 INPUT
data_o[56:0] Yes Yes T2,T4,T16 Yes T2,T36,T4 OUTPUT
syndrome_o[6:0] Yes Yes T2,T16,T14 Yes T2,T49,T50 OUTPUT
err_o[1:0] Yes Yes T2,T4,T5 Yes T2,T16,T14 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%