Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	209399	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	576836	1		T5	2		T6	4		T7	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	496973	1		T13	10		T16	80		T20	4
values[0x0]	142845	1		T5	2		T6	11		T7	6
values[0x1]	146417	1		T5	4		T6	9		T7	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159400	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	626835	1		T5	3		T6	4		T7	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2811	1		T54	2		T46	42		T53	26
valid_sources[0x01]	2823	1		T45	1		T46	43		T53	4
valid_sources[0x02]	3069	1		T13	1		T17	3		T15	5
valid_sources[0x03]	3266	1		T17	2		T12	5		T46	38
valid_sources[0x04]	2886	1		T45	140		T46	43		T53	36
valid_sources[0x05]	2946	1		T28	1		T17	2		T11	4
valid_sources[0x06]	2592	1		T17	1		T46	46		T53	24
valid_sources[0x07]	3574	1		T6	1		T33	1		T46	49
valid_sources[0x08]	3588	1		T11	1		T54	2		T46	42
valid_sources[0x09]	2876	1		T12	4		T46	42		T53	20
valid_sources[0x0a]	2854	1		T12	2		T46	41		T53	27
valid_sources[0x0b]	2929	1		T15	1		T46	50		T53	7
valid_sources[0x0c]	3013	1		T54	8		T46	44		T53	34
valid_sources[0x0d]	3079	1		T46	44		T53	17		T71	8
valid_sources[0x0e]	3016	1		T12	1		T46	27		T53	14
valid_sources[0x0f]	2521	1		T28	1		T54	3		T46	45
valid_sources[0x10]	2996	1		T54	3		T46	35		T53	18
valid_sources[0x11]	2757	1		T12	1		T46	47		T53	32
valid_sources[0x12]	3431	1		T23	1		T54	1		T46	42
valid_sources[0x13]	3098	1		T33	1		T54	1		T46	63
valid_sources[0x14]	3076	1		T46	44		T53	35		T71	2
valid_sources[0x15]	3700	1		T135	3		T54	7		T46	29
valid_sources[0x16]	2735	1		T54	6		T46	37		T53	31
valid_sources[0x17]	3369	1		T16	1		T12	1		T46	56
valid_sources[0x18]	3271	1		T135	1		T54	1		T46	34
valid_sources[0x19]	4029	1		T46	53		T53	5		T71	6
valid_sources[0x1a]	2906	1		T6	1		T16	1		T17	1
valid_sources[0x1b]	2977	1		T16	1		T27	2		T46	49
valid_sources[0x1c]	3234	1		T7	8		T10	1		T54	2
valid_sources[0x1d]	3270	1		T54	4		T46	36		T53	22
valid_sources[0x1e]	2942	1		T28	1		T11	1		T12	1
valid_sources[0x1f]	2692	1		T6	2		T17	1		T23	1
valid_sources[0x20]	3075	1		T46	37		T53	26		T71	28
valid_sources[0x21]	2731	1		T54	8		T46	40		T53	30
valid_sources[0x22]	3147	1		T17	1		T46	43		T53	5
valid_sources[0x23]	2892	1		T46	49		T53	17		T71	38
valid_sources[0x24]	3179	1		T54	4		T46	54		T53	19
valid_sources[0x25]	2789	1		T54	3		T45	1		T46	56
valid_sources[0x26]	2960	1		T54	19		T46	38		T53	10
valid_sources[0x27]	2973	1		T17	1		T45	3		T46	39
valid_sources[0x28]	3075	1		T46	42		T53	2		T71	15
valid_sources[0x29]	3071	1		T32	3		T45	2		T46	55
valid_sources[0x2a]	2792	1		T17	1		T46	37		T53	18
valid_sources[0x2b]	3878	1		T13	1		T16	3		T17	1
valid_sources[0x2c]	2899	1		T6	1		T16	5		T46	42
valid_sources[0x2d]	2761	1		T54	6		T45	9		T46	41
valid_sources[0x2e]	2978	1		T45	4		T46	45		T53	18
valid_sources[0x2f]	3318	1		T12	1		T46	50		T53	7
valid_sources[0x30]	2720	1		T32	4		T46	47		T53	6
valid_sources[0x31]	2918	1		T46	32		T53	30		T71	22
valid_sources[0x32]	2499	1		T54	5		T46	41		T53	32
valid_sources[0x33]	2552	1		T46	34		T53	17		T71	38
valid_sources[0x34]	3220	1		T6	1		T46	39		T53	5
valid_sources[0x35]	3148	1		T12	1		T45	2		T46	56
valid_sources[0x36]	3000	1		T6	1		T23	3		T46	41
valid_sources[0x37]	2953	1		T54	20		T46	40		T53	9
valid_sources[0x38]	2801	1		T16	2		T46	34		T53	21
valid_sources[0x39]	2452	1		T46	44		T53	23		T72	16
valid_sources[0x3a]	3073	1		T46	52		T53	28		T71	6
valid_sources[0x3b]	2781	1		T16	2		T54	12		T46	58
valid_sources[0x3c]	3044	1		T17	2		T54	2		T46	26
valid_sources[0x3d]	2892	1		T6	1		T17	2		T46	45
valid_sources[0x3e]	3140	1		T54	27		T46	46		T53	7
valid_sources[0x3f]	2918	1		T54	3		T46	52		T53	15
valid_sources[0x40]	2673	1		T12	2		T46	36		T53	17
valid_sources[0x41]	2742	1		T13	1		T11	3		T46	46
valid_sources[0x42]	2907	1		T16	1		T45	1		T46	43
valid_sources[0x43]	3151	1		T46	45		T53	32		T71	22
valid_sources[0x44]	2608	1		T16	5		T23	2		T54	1
valid_sources[0x45]	3069	1		T16	1		T54	8		T45	7
valid_sources[0x46]	2828	1		T32	1		T54	20		T46	46
valid_sources[0x47]	2620	1		T17	1		T46	41		T53	21
valid_sources[0x48]	2640	1		T12	1		T46	38		T53	20
valid_sources[0x49]	3228	1		T6	1		T54	1		T46	59
valid_sources[0x4a]	3048	1		T12	1		T46	39		T53	11
valid_sources[0x4b]	2676	1		T29	1		T32	2		T54	15
valid_sources[0x4c]	3174	1		T16	1		T46	34		T53	11
valid_sources[0x4d]	3014	1		T16	1		T17	5		T54	2
valid_sources[0x4e]	2846	1		T54	11		T46	44		T53	16
valid_sources[0x4f]	2694	1		T17	2		T12	1		T46	49
valid_sources[0x50]	3712	1		T16	2		T54	6		T46	49
valid_sources[0x51]	2735	1		T54	15		T46	49		T53	16
valid_sources[0x52]	2923	1		T54	1		T45	9		T46	46
valid_sources[0x53]	3771	1		T54	3		T46	40		T53	31
valid_sources[0x54]	3139	1		T16	1		T11	2		T46	46
valid_sources[0x55]	2773	1		T13	1		T54	1		T46	43
valid_sources[0x56]	2968	1		T5	1		T6	1		T46	46
valid_sources[0x57]	3118	1		T16	1		T54	1		T46	37
valid_sources[0x58]	2954	1		T6	1		T17	1		T12	3
valid_sources[0x59]	3378	1		T32	2		T54	6		T46	51
valid_sources[0x5a]	2942	1		T46	35		T53	11		T71	18
valid_sources[0x5b]	3020	1		T17	3		T29	1		T46	51
valid_sources[0x5c]	3117	1		T54	7		T46	33		T53	16
valid_sources[0x5d]	3354	1		T54	3		T46	37		T53	12
valid_sources[0x5e]	3017	1		T46	38		T53	28		T71	40
valid_sources[0x5f]	3109	1		T33	5		T46	46		T53	26
valid_sources[0x60]	3977	1		T46	40		T53	21		T72	10
valid_sources[0x61]	3334	1		T16	3		T46	52		T53	21
valid_sources[0x62]	4307	1		T46	47		T53	3		T72	12
valid_sources[0x63]	3191	1		T12	1		T46	34		T53	8
valid_sources[0x64]	2575	1		T13	1		T54	1		T45	2
valid_sources[0x65]	3033	1		T6	1		T46	46		T53	19
valid_sources[0x66]	3134	1		T17	1		T11	1		T46	44
valid_sources[0x67]	2718	1		T5	1		T46	52		T53	15
valid_sources[0x68]	3225	1		T46	53		T53	30		T71	51
valid_sources[0x69]	2693	1		T46	29		T53	23		T71	42
valid_sources[0x6a]	3388	1		T17	1		T46	35		T53	9
valid_sources[0x6b]	3062	1		T46	54		T53	39		T71	9
valid_sources[0x6c]	3012	1		T17	3		T46	45		T53	9
valid_sources[0x6d]	3099	1		T23	1		T54	4		T45	1
valid_sources[0x6e]	2843	1		T46	47		T53	21		T71	17
valid_sources[0x6f]	3005	1		T20	1		T15	1		T46	47
valid_sources[0x70]	3176	1		T11	2		T46	42		T53	12
valid_sources[0x71]	3191	1		T46	38		T53	30		T71	15
valid_sources[0x72]	2684	1		T46	46		T53	18		T71	14
valid_sources[0x73]	2513	1		T15	1		T54	9		T46	27
valid_sources[0x74]	2807	1		T6	1		T46	34		T53	50
valid_sources[0x75]	2720	1		T5	1		T16	1		T46	29
valid_sources[0x76]	3097	1		T11	2		T46	35		T53	32
valid_sources[0x77]	2856	1		T29	1		T54	11		T46	38
valid_sources[0x78]	2764	1		T6	1		T46	48		T53	6
valid_sources[0x79]	2661	1		T12	1		T46	34		T53	14
valid_sources[0x7a]	3212	1		T6	1		T10	9		T46	49
valid_sources[0x7b]	3676	1		T16	2		T28	1		T12	1
valid_sources[0x7c]	2672	1		T46	42		T53	1		T71	25
valid_sources[0x7d]	3439	1		T17	1		T22	1		T45	1
valid_sources[0x7e]	3075	1		T17	3		T46	31		T53	37
valid_sources[0x7f]	3059	1		T6	1		T16	1		T46	51
valid_sources[0x80]	3228	1		T14	7		T15	1		T45	142

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

295278

1

T13

4

T16

80

T20

4

values[0x0]

all_enables

biggest_size

141167

1

T6

2

T7

1

T19

1

values[0x1]

all_enables

biggest_size

140391

1

T5

2

T6

2

T7

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5204	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18627	1		T1	3		T39	2		T40	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9928	1		T54	219		T45	127		T46	66
values[0x0]	6911	1		T1	3		T39	4		T40	3
values[0x1]	6992	1		T1	6		T39	4		T40	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3982	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19849	1		T1	4		T39	2		T40	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	102	1		T136	2		T54	3		T45	2
valid_sources[0x01]	64	1		T54	3		T45	5		T63	3
valid_sources[0x02]	82	1		T54	5		T45	2		T63	4
valid_sources[0x03]	69	1		T54	1		T45	1		T67	4
valid_sources[0x04]	206	1		T54	3		T45	1		T71	1
valid_sources[0x05]	80	1		T54	1		T45	1		T46	3
valid_sources[0x06]	126	1		T137	3		T138	10		T54	5
valid_sources[0x07]	68	1		T139	1		T45	2		T53	2
valid_sources[0x08]	59	1		T55	1		T140	3		T54	2
valid_sources[0x09]	101	1		T1	1		T54	1		T45	3
valid_sources[0x0a]	67	1		T45	1		T63	2		T67	2
valid_sources[0x0b]	78	1		T54	3		T45	1		T64	1
valid_sources[0x0c]	78	1		T141	1		T54	2		T76	1
valid_sources[0x0d]	189	1		T142	19		T54	3		T45	6
valid_sources[0x0e]	77	1		T1	2		T54	4		T63	5
valid_sources[0x0f]	61	1		T54	5		T45	5		T67	1
valid_sources[0x10]	70	1		T54	3		T45	2		T63	2
valid_sources[0x11]	85	1		T54	5		T45	3		T72	1
valid_sources[0x12]	104	1		T143	1		T144	1		T54	3
valid_sources[0x13]	58	1		T56	1		T145	1		T54	5
valid_sources[0x14]	74	1		T54	1		T45	2		T63	2
valid_sources[0x15]	92	1		T146	2		T147	1		T54	3
valid_sources[0x16]	88	1		T62	1		T54	3		T63	4
valid_sources[0x17]	72	1		T54	2		T72	2		T63	2
valid_sources[0x18]	73	1		T54	3		T45	1		T64	4
valid_sources[0x19]	67	1		T148	1		T54	5		T45	1
valid_sources[0x1a]	79	1		T146	1		T54	2		T47	2
valid_sources[0x1b]	104	1		T54	7		T45	2		T66	3
valid_sources[0x1c]	99	1		T54	1		T45	1		T47	3
valid_sources[0x1d]	90	1		T149	2		T54	12		T45	4
valid_sources[0x1e]	86	1		T54	3		T45	1		T53	3
valid_sources[0x1f]	84	1		T54	2		T45	2		T63	1
valid_sources[0x20]	74	1		T54	2		T45	7		T47	1
valid_sources[0x21]	97	1		T150	18		T151	1		T54	1
valid_sources[0x22]	94	1		T148	1		T54	5		T45	3
valid_sources[0x23]	257	1		T54	5		T64	1		T66	8
valid_sources[0x24]	90	1		T54	1		T45	3		T46	3
valid_sources[0x25]	81	1		T54	2		T45	1		T71	2
valid_sources[0x26]	92	1		T45	2		T47	2		T68	5
valid_sources[0x27]	97	1		T54	3		T45	4		T72	1
valid_sources[0x28]	99	1		T117	1		T152	10		T54	9
valid_sources[0x29]	80	1		T54	5		T45	2		T47	1
valid_sources[0x2a]	87	1		T54	6		T73	1		T64	1
valid_sources[0x2b]	121	1		T61	19		T54	5		T45	2
valid_sources[0x2c]	79	1		T153	1		T154	1		T54	3
valid_sources[0x2d]	120	1		T55	1		T116	1		T117	2
valid_sources[0x2e]	107	1		T1	1		T54	3		T45	5
valid_sources[0x2f]	93	1		T55	2		T54	2		T45	5
valid_sources[0x30]	78	1		T54	2		T45	5		T71	1
valid_sources[0x31]	96	1		T54	4		T45	2		T46	3
valid_sources[0x32]	107	1		T155	2		T54	5		T45	3
valid_sources[0x33]	89	1		T156	6		T54	2		T45	4
valid_sources[0x34]	59	1		T54	3		T64	2		T76	1
valid_sources[0x35]	65	1		T39	4		T149	1		T139	5
valid_sources[0x36]	59	1		T146	1		T147	1		T54	5
valid_sources[0x37]	68	1		T54	6		T45	3		T71	1
valid_sources[0x38]	72	1		T55	1		T155	1		T54	2
valid_sources[0x39]	82	1		T54	3		T45	1		T64	1
valid_sources[0x3a]	111	1		T154	1		T54	8		T45	2
valid_sources[0x3b]	69	1		T54	2		T45	2		T53	1
valid_sources[0x3c]	93	1		T146	1		T54	3		T45	1
valid_sources[0x3d]	123	1		T45	2		T53	10		T71	1
valid_sources[0x3e]	108	1		T54	1		T45	3		T64	2
valid_sources[0x3f]	96	1		T60	1		T144	5		T54	2
valid_sources[0x40]	112	1		T157	18		T54	7		T45	2
valid_sources[0x41]	65	1		T39	1		T62	1		T54	3
valid_sources[0x42]	71	1		T54	4		T72	1		T67	4
valid_sources[0x43]	124	1		T54	2		T45	4		T72	2
valid_sources[0x44]	92	1		T54	8		T45	1		T46	3
valid_sources[0x45]	61	1		T54	3		T64	2		T67	1
valid_sources[0x46]	148	1		T54	3		T45	1		T63	1
valid_sources[0x47]	98	1		T54	6		T64	1		T66	1
valid_sources[0x48]	104	1		T54	2		T45	4		T53	1
valid_sources[0x49]	73	1		T144	1		T54	2		T45	1
valid_sources[0x4a]	103	1		T54	8		T45	2		T53	1
valid_sources[0x4b]	83	1		T54	1		T45	1		T71	4
valid_sources[0x4c]	66	1		T146	1		T54	2		T45	4
valid_sources[0x4d]	76	1		T158	1		T54	2		T45	1
valid_sources[0x4e]	67	1		T54	2		T45	1		T53	1
valid_sources[0x4f]	104	1		T54	8		T45	1		T63	3
valid_sources[0x50]	71	1		T54	1		T45	3		T63	1
valid_sources[0x51]	112	1		T55	3		T141	1		T54	4
valid_sources[0x52]	93	1		T54	3		T67	1		T77	3
valid_sources[0x53]	77	1		T159	1		T139	1		T54	8
valid_sources[0x54]	148	1		T54	2		T45	3		T63	3
valid_sources[0x55]	137	1		T143	4		T147	1		T54	3
valid_sources[0x56]	109	1		T55	1		T155	2		T54	2
valid_sources[0x57]	68	1		T147	1		T54	4		T45	3
valid_sources[0x58]	84	1		T54	2		T45	2		T47	1
valid_sources[0x59]	61	1		T54	4		T45	1		T71	2
valid_sources[0x5a]	76	1		T59	5		T54	4		T45	1
valid_sources[0x5b]	70	1		T155	1		T54	2		T45	2
valid_sources[0x5c]	78	1		T147	1		T54	4		T45	1
valid_sources[0x5d]	62	1		T137	2		T54	3		T53	1
valid_sources[0x5e]	105	1		T54	2		T45	3		T63	1
valid_sources[0x5f]	78	1		T147	1		T154	1		T54	5
valid_sources[0x60]	105	1		T54	9		T45	3		T71	5
valid_sources[0x61]	91	1		T54	1		T45	3		T47	1
valid_sources[0x62]	102	1		T145	1		T54	2		T45	5
valid_sources[0x63]	63	1		T136	1		T54	2		T45	1
valid_sources[0x64]	123	1		T147	1		T54	3		T45	4
valid_sources[0x65]	103	1		T147	1		T54	1		T45	3
valid_sources[0x66]	78	1		T56	4		T54	7		T45	1
valid_sources[0x67]	75	1		T136	1		T137	3		T54	2
valid_sources[0x68]	114	1		T160	1		T54	6		T47	2
valid_sources[0x69]	276	1		T161	1		T54	4		T53	1
valid_sources[0x6a]	245	1		T54	2		T53	1		T47	4
valid_sources[0x6b]	119	1		T55	1		T54	2		T45	2
valid_sources[0x6c]	91	1		T156	2		T54	4		T45	2
valid_sources[0x6d]	65	1		T54	6		T45	1		T64	1
valid_sources[0x6e]	86	1		T54	3		T45	2		T71	1
valid_sources[0x6f]	100	1		T54	4		T47	2		T64	3
valid_sources[0x70]	69	1		T54	3		T45	2		T67	3
valid_sources[0x71]	115	1		T116	1		T54	7		T45	3
valid_sources[0x72]	82	1		T54	6		T46	3		T63	1
valid_sources[0x73]	82	1		T155	2		T54	1		T45	2
valid_sources[0x74]	125	1		T143	1		T54	4		T45	5
valid_sources[0x75]	75	1		T54	3		T45	3		T72	6
valid_sources[0x76]	84	1		T54	3		T45	1		T63	5
valid_sources[0x77]	74	1		T54	2		T45	2		T71	1
valid_sources[0x78]	93	1		T54	5		T45	1		T64	2
valid_sources[0x79]	86	1		T54	2		T45	4		T63	1
valid_sources[0x7a]	101	1		T55	1		T54	2		T45	1
valid_sources[0x7b]	78	1		T54	5		T45	2		T63	2
valid_sources[0x7c]	85	1		T117	3		T146	1		T54	2
valid_sources[0x7d]	96	1		T57	2		T116	3		T162	10
valid_sources[0x7e]	99	1		T54	2		T45	2		T63	3
valid_sources[0x7f]	74	1		T54	3		T45	1		T67	1
valid_sources[0x80]	67	1		T161	5		T54	4		T45	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6712

1

T54

215

T45

124

T46

30

values[0x0]

all_enables

biggest_size

6130

1

T1

2

T39

1

T40

1

values[0x1]

all_enables

biggest_size

5785

1

T1

1

T39

1

T40

1