SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 802585 | 1 | T5 | 6 | T6 | 20 | T7 | 20 | |||
auto[1] | 17767 | 1 | T16 | 80 | T17 | 80 | T54 | 892 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 820125 | 1 | T5 | 6 | T6 | 20 | T7 | 20 | |||
values[1] | 25 | 1 | T46 | 1 | T53 | 1 | T66 | 2 | |||
values[2] | 5 | 1 | T46 | 2 | T68 | 1 | T126 | 1 | |||
values[3] | 125 | 1 | T46 | 5 | T53 | 3 | T66 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 820112 | 1 | T5 | 6 | T6 | 20 | T7 | 20 | |||
values[1] | 20 | 1 | T53 | 2 | T66 | 2 | T132 | 1 | |||
values[2] | 11 | 1 | T46 | 1 | T53 | 1 | T66 | 1 | |||
values[3] | 122 | 1 | T46 | 10 | T53 | 2 | T66 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 820002 | 1 | T5 | 6 | T6 | 20 | T7 | 20 | |||
auto[TlIntgErrCmd] | 110 | 1 | T46 | 5 | T53 | 3 | T66 | 6 | |||
auto[TlIntgErrData] | 123 | 1 | T46 | 5 | T53 | 3 | T66 | 9 | |||
auto[TlIntgErrBoth] | 117 | 1 | T46 | 10 | T53 | 4 | T66 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 39533 | 0 | T1 | 9 | T39 | 8 | T40 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39306 | 1 | T1 | 9 | T39 | 8 | T40 | 6 | |||
values[1] | 24 | 1 | T46 | 1 | T53 | 1 | T66 | 3 | |||
values[2] | 3 | 1 | T46 | 1 | T68 | 1 | T128 | 1 | |||
values[3] | 126 | 1 | T46 | 5 | T53 | 3 | T66 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39290 | 1 | T1 | 9 | T39 | 8 | T40 | 6 | |||
values[1] | 16 | 1 | T66 | 2 | T119 | 2 | T132 | 1 | |||
values[2] | 13 | 1 | T53 | 3 | T126 | 2 | T131 | 1 | |||
values[3] | 118 | 1 | T46 | 5 | T53 | 2 | T66 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 39183 | 1 | T1 | 9 | T39 | 8 | T40 | 6 | |||
auto[TlIntgErrCmd] | 107 | 1 | T46 | 10 | T53 | 1 | T66 | 7 | |||
auto[TlIntgErrData] | 123 | 1 | T46 | 4 | T53 | 4 | T66 | 6 | |||
auto[TlIntgErrBoth] | 120 | 1 | T46 | 6 | T53 | 5 | T66 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |