Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	242168	1		T5	4		T6	16		T7	17
full_word	578184	1		T5	2		T6	4		T7	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	820002	1		T5	6		T6	20		T7	20
auto[TlIntgErrCmd]	110	1		T46	5		T53	3		T66	6
auto[TlIntgErrData]	123	1		T46	5		T53	3		T66	9
auto[TlIntgErrBoth]	117	1		T46	10		T53	4		T66	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	498553	1		T13	10		T16	80		T20	4
auto[1]	321799	1		T5	6		T6	20		T7	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	202986	1		T13	6		T27	5		T28	3
auto[TlIntgErrNone]	partial	auto[1]	38852	1		T5	4		T6	16		T7	17
auto[TlIntgErrNone]	full_word	auto[0]	295419	1		T13	4		T16	80		T20	4
auto[TlIntgErrNone]	full_word	auto[1]	282745	1		T5	2		T6	4		T7	3
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T46	2		T53	1		T66	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T46	3		T53	2		T66	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T68	1		T126	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T46	1		T53	1		T66	3
auto[TlIntgErrData]	partial	auto[1]	67	1		T46	4		T53	1		T66	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T53	1		T128	1		T129	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T66	2		T130	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T46	2		T66	1		T68	3
auto[TlIntgErrBoth]	partial	auto[1]	65	1		T46	7		T53	3		T66	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T46	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T53	1		T66	1		T68	1