Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.33	96.97	55.32	86.87		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	21814326	12460	0	0
late_debug_enable_rd_A	21814326	2820	0	0
late_debug_enable_regwen_rd_A	21814326	2453	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21814326	12460	0	0
T45	599448	158	0	0
T46	80425	2	0	0
T47	299748	47	0	0
T54	8401	577	0	0
T63	65608	55	0	0
T64	9861	438	0	0
T66	84242	1	0	0
T67	8709	504	0	0
T68	31689	6	0	0
T69	238115	255	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21814326	2820	0	0
T66	84242	66	0	0
T70	17394	317	0	0
T73	44237	42	0	0
T75	9706	1	0	0
T79	19977	20	0	0
T82	7716	41	0	0
T94	5917	5	0	0
T118	59682	43	0	0
T119	78418	32	0	0
T120	9526	72	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21814326	2453	0	0
T66	84242	73	0	0
T70	17394	220	0	0
T73	44237	37	0	0
T75	9706	1	0	0
T79	19977	18	0	0
T82	7716	11	0	0
T94	5917	7	0	0
T118	59682	54	0	0
T119	78418	48	0	0
T120	9526	56	0	0