Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8964329 |
8963523 |
0 |
0 |
selKnown1 |
9373440 |
9372634 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8964329 |
8963523 |
0 |
0 |
T1 |
310 |
308 |
0 |
0 |
T2 |
7510 |
7506 |
0 |
0 |
T3 |
3350 |
3346 |
0 |
0 |
T4 |
3994 |
3990 |
0 |
0 |
T5 |
5080 |
5076 |
0 |
0 |
T6 |
13412 |
13408 |
0 |
0 |
T8 |
1156 |
1152 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T18 |
3818 |
3814 |
0 |
0 |
T24 |
0 |
9 |
0 |
0 |
T30 |
1734 |
1730 |
0 |
0 |
T31 |
3558 |
3554 |
0 |
0 |
T34 |
2 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T38 |
0 |
40 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9373440 |
9372634 |
0 |
0 |
T1 |
2337 |
2335 |
0 |
0 |
T2 |
94993 |
94989 |
0 |
0 |
T3 |
6636 |
6632 |
0 |
0 |
T4 |
6044 |
6040 |
0 |
0 |
T5 |
10808 |
10804 |
0 |
0 |
T6 |
24641 |
24637 |
0 |
0 |
T8 |
3400 |
3396 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T18 |
12946 |
12942 |
0 |
0 |
T24 |
0 |
8 |
0 |
0 |
T30 |
8793 |
8789 |
0 |
0 |
T31 |
4101 |
4097 |
0 |
0 |
T34 |
2 |
0 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T38 |
0 |
40 |
0 |
0 |
T42 |
0 |
20 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T45 |
0 |
38 |
0 |
0 |
T46 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1183540 |
1183441 |
0 |
0 |
selKnown1 |
1592730 |
1592631 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1183540 |
1183441 |
0 |
0 |
T1 |
155 |
154 |
0 |
0 |
T2 |
3734 |
3733 |
0 |
0 |
T3 |
1674 |
1673 |
0 |
0 |
T4 |
1986 |
1985 |
0 |
0 |
T5 |
2539 |
2538 |
0 |
0 |
T6 |
6705 |
6704 |
0 |
0 |
T8 |
577 |
576 |
0 |
0 |
T18 |
1908 |
1907 |
0 |
0 |
T30 |
866 |
865 |
0 |
0 |
T31 |
1778 |
1777 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1592730 |
1592631 |
0 |
0 |
T1 |
2182 |
2181 |
0 |
0 |
T2 |
91217 |
91216 |
0 |
0 |
T3 |
4960 |
4959 |
0 |
0 |
T4 |
4036 |
4035 |
0 |
0 |
T5 |
8267 |
8266 |
0 |
0 |
T6 |
17934 |
17933 |
0 |
0 |
T8 |
2821 |
2820 |
0 |
0 |
T18 |
11036 |
11035 |
0 |
0 |
T30 |
7925 |
7924 |
0 |
0 |
T31 |
2321 |
2320 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
178 |
79 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T42 |
0 |
10 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
177 |
78 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T42 |
0 |
10 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7779109 |
7778805 |
0 |
0 |
selKnown1 |
7779109 |
7778805 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7779109 |
7778805 |
0 |
0 |
T1 |
155 |
154 |
0 |
0 |
T2 |
3734 |
3733 |
0 |
0 |
T3 |
1674 |
1673 |
0 |
0 |
T4 |
1986 |
1985 |
0 |
0 |
T5 |
2539 |
2538 |
0 |
0 |
T6 |
6705 |
6704 |
0 |
0 |
T8 |
577 |
576 |
0 |
0 |
T18 |
1908 |
1907 |
0 |
0 |
T30 |
866 |
865 |
0 |
0 |
T31 |
1778 |
1777 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7779109 |
7778805 |
0 |
0 |
T1 |
155 |
154 |
0 |
0 |
T2 |
3734 |
3733 |
0 |
0 |
T3 |
1674 |
1673 |
0 |
0 |
T4 |
1986 |
1985 |
0 |
0 |
T5 |
2539 |
2538 |
0 |
0 |
T6 |
6705 |
6704 |
0 |
0 |
T8 |
577 |
576 |
0 |
0 |
T18 |
1908 |
1907 |
0 |
0 |
T30 |
866 |
865 |
0 |
0 |
T31 |
1778 |
1777 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1502 |
1198 |
0 |
0 |
selKnown1 |
1424 |
1120 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1502 |
1198 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T24 |
0 |
5 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T41 |
0 |
8 |
0 |
0 |
T42 |
0 |
10 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1424 |
1120 |
0 |
0 |
T2 |
21 |
20 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T24 |
0 |
4 |
0 |
0 |
T30 |
1 |
0 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T42 |
0 |
10 |
0 |
0 |
T44 |
0 |
10 |
0 |
0 |
T45 |
0 |
38 |
0 |
0 |
T46 |
0 |
40 |
0 |
0 |