Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T1,*T4,*T34 |
Yes |
T1,T8,T4 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T4,T6 |
Yes |
T1,T5,T4 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T4,T34 |
Yes |
T1,T8,T4 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T1,T4,T34 |
Yes |
T1,T4,T34 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T8,T4 |
Yes |
T1,T4,T34 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
154 |
59.23 |
Total Bits 0->1 |
130 |
77 |
59.23 |
Total Bits 1->0 |
130 |
77 |
59.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
154 |
59.23 |
Port Bits 0->1 |
130 |
77 |
59.23 |
Port Bits 1->0 |
130 |
77 |
59.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[3:0] |
Yes |
Yes |
T34,T24,*T35 |
Yes |
T34,T24,T35 |
INPUT |
data_i[56:4] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T34,T24,T35 |
Yes |
T6,T34,T24 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T34,T24,T35 |
Yes |
T34,T24,T35 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T34,T24,T35 |
Yes |
T34,T24,T35 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T34,T24,T35 |
Yes |
T34,T24,T35 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T1,*T4,*T39 |
Yes |
T1,T4,T39 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T4,T39 |
Yes |
T1,T4,T39 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T4,T39 |
Yes |
T1,T4,T39 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T1,T4,T39 |
Yes |
T1,T4,T39 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T4,T39 |
Yes |
T1,T4,T39 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T7,*T13,*T20 |
Yes |
T8,T5,T6 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T6,T7,T13 |
Yes |
T1,T5,T18 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T7,T13,T20 |
Yes |
T8,T5,T6 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T7,T14,T17 |
Yes |
T1,T7,T59 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T8,T5 |
Yes |
T7,T20,T14 |
OUTPUT |
*Tests covering at least one bit in the range