Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	180192	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	489952	1		T4	31		T5	15		T12	80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	438132	1		T4	10		T5	18		T12	80
values[0x0]	113864	1		T4	48		T5	16		T7	1
values[0x1]	118148	1		T4	47		T5	15		T6	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136221	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	533923	1		T4	41		T5	20		T12	80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2312	1		T4	1		T26	1		T31	2
valid_sources[0x01]	2892	1		T4	1		T11	1		T26	7
valid_sources[0x02]	3123	1		T11	1		T26	9		T31	12
valid_sources[0x03]	2476	1		T11	1		T26	2		T29	4
valid_sources[0x04]	2458	1		T6	2		T26	7		T31	4
valid_sources[0x05]	2816	1		T26	13		T31	1		T29	1
valid_sources[0x06]	2492	1		T6	1		T11	1		T26	4
valid_sources[0x07]	2589	1		T4	1		T11	1		T26	4
valid_sources[0x08]	2219	1		T11	1		T26	2		T31	2
valid_sources[0x09]	3213	1		T26	10		T31	1		T29	3
valid_sources[0x0a]	2936	1		T11	1		T26	12		T31	2
valid_sources[0x0b]	4269	1		T4	2		T26	2		T31	5
valid_sources[0x0c]	2653	1		T4	1		T13	10		T26	7
valid_sources[0x0d]	2724	1		T26	6		T31	10		T29	4
valid_sources[0x0e]	2514	1		T13	2		T26	10		T31	2
valid_sources[0x0f]	2879	1		T4	1		T6	1		T10	1
valid_sources[0x10]	2359	1		T4	1		T26	2		T31	5
valid_sources[0x11]	2565	1		T12	1		T6	3		T26	5
valid_sources[0x12]	2667	1		T4	1		T11	2		T26	1
valid_sources[0x13]	2033	1		T26	12		T31	2		T29	4
valid_sources[0x14]	2670	1		T26	3		T31	2		T29	1
valid_sources[0x15]	2611	1		T4	1		T10	5		T26	22
valid_sources[0x16]	3184	1		T4	1		T10	1		T26	8
valid_sources[0x17]	2777	1		T12	3		T11	1		T26	7
valid_sources[0x18]	2205	1		T7	1		T6	1		T26	3
valid_sources[0x19]	2619	1		T11	3		T26	2		T31	3
valid_sources[0x1a]	2896	1		T4	1		T11	1		T26	6
valid_sources[0x1b]	2598	1		T4	2		T6	2		T11	2
valid_sources[0x1c]	2416	1		T26	10		T29	6		T52	22
valid_sources[0x1d]	2287	1		T26	1		T31	4		T29	3
valid_sources[0x1e]	2593	1		T12	1		T6	2		T26	2
valid_sources[0x1f]	2204	1		T4	2		T12	2		T6	2
valid_sources[0x20]	2491	1		T11	3		T26	5		T29	2
valid_sources[0x21]	2464	1		T11	2		T26	3		T31	2
valid_sources[0x22]	2687	1		T26	11		T31	16		T29	4
valid_sources[0x23]	2255	1		T4	1		T12	2		T26	10
valid_sources[0x24]	2478	1		T26	5		T31	4		T29	2
valid_sources[0x25]	2314	1		T6	5		T26	3		T31	1
valid_sources[0x26]	2584	1		T31	1		T29	2		T27	4
valid_sources[0x27]	2383	1		T4	1		T26	9		T31	3
valid_sources[0x28]	2332	1		T6	1		T26	6		T31	10
valid_sources[0x29]	2536	1		T6	2		T10	2		T26	9
valid_sources[0x2a]	2983	1		T12	7		T13	5		T11	1
valid_sources[0x2b]	3174	1		T7	1		T26	11		T29	2
valid_sources[0x2c]	2580	1		T4	2		T13	4		T26	4
valid_sources[0x2d]	2791	1		T4	2		T26	5		T31	2
valid_sources[0x2e]	2946	1		T4	1		T12	1		T29	1
valid_sources[0x2f]	2473	1		T4	1		T26	5		T31	1
valid_sources[0x30]	2543	1		T31	1		T52	15		T66	16
valid_sources[0x31]	3069	1		T30	275		T26	3		T31	5
valid_sources[0x32]	2378	1		T6	1		T26	21		T31	22
valid_sources[0x33]	3247	1		T6	2		T26	6		T31	19
valid_sources[0x34]	2509	1		T4	1		T11	1		T26	3
valid_sources[0x35]	2277	1		T4	1		T11	2		T26	16
valid_sources[0x36]	2452	1		T6	3		T11	1		T26	5
valid_sources[0x37]	2557	1		T26	1		T31	4		T29	3
valid_sources[0x38]	2823	1		T26	2		T31	9		T29	4
valid_sources[0x39]	2311	1		T6	2		T10	6		T26	2
valid_sources[0x3a]	2445	1		T13	6		T26	4		T31	1
valid_sources[0x3b]	3072	1		T4	1		T26	1		T29	2
valid_sources[0x3c]	2382	1		T7	1		T6	1		T26	18
valid_sources[0x3d]	2110	1		T26	3		T29	5		T52	26
valid_sources[0x3e]	2182	1		T6	3		T11	1		T26	2
valid_sources[0x3f]	2507	1		T12	2		T11	1		T26	12
valid_sources[0x40]	2499	1		T26	14		T31	2		T29	4
valid_sources[0x41]	2383	1		T12	2		T6	1		T10	1
valid_sources[0x42]	2710	1		T4	1		T16	9		T26	1
valid_sources[0x43]	2580	1		T6	1		T26	6		T29	3
valid_sources[0x44]	2211	1		T6	1		T26	12		T31	1
valid_sources[0x45]	2222	1		T10	1		T26	9		T31	4
valid_sources[0x46]	2785	1		T4	1		T12	3		T6	4
valid_sources[0x47]	2461	1		T26	1		T29	3		T52	36
valid_sources[0x48]	2428	1		T4	1		T6	2		T26	5
valid_sources[0x49]	2265	1		T26	8		T29	3		T52	32
valid_sources[0x4a]	2607	1		T12	1		T13	3		T26	11
valid_sources[0x4b]	2629	1		T26	4		T31	9		T29	5
valid_sources[0x4c]	3131	1		T12	1		T26	4		T29	4
valid_sources[0x4d]	2323	1		T13	1		T11	1		T26	12
valid_sources[0x4e]	2549	1		T26	7		T29	1		T52	25
valid_sources[0x4f]	2843	1		T4	1		T12	2		T65	103
valid_sources[0x50]	2326	1		T4	1		T26	2		T31	1
valid_sources[0x51]	2303	1		T6	3		T26	5		T31	2
valid_sources[0x52]	2593	1		T26	6		T31	5		T29	2
valid_sources[0x53]	2543	1		T10	1		T31	1		T29	3
valid_sources[0x54]	2496	1		T26	22		T31	8		T29	4
valid_sources[0x55]	2410	1		T6	1		T29	4		T52	21
valid_sources[0x56]	2486	1		T4	2		T11	1		T29	3
valid_sources[0x57]	2359	1		T26	4		T31	4		T29	6
valid_sources[0x58]	2309	1		T4	1		T12	2		T10	2
valid_sources[0x59]	2443	1		T4	1		T6	1		T10	1
valid_sources[0x5a]	3011	1		T12	1		T11	1		T31	2
valid_sources[0x5b]	2790	1		T26	5		T31	1		T29	1
valid_sources[0x5c]	2781	1		T6	2		T10	3		T11	1
valid_sources[0x5d]	2545	1		T6	1		T11	1		T31	2
valid_sources[0x5e]	2425	1		T6	1		T11	2		T31	6
valid_sources[0x5f]	2307	1		T10	4		T26	4		T31	1
valid_sources[0x60]	2166	1		T11	1		T26	1		T29	1
valid_sources[0x61]	2668	1		T12	1		T26	20		T29	3
valid_sources[0x62]	2567	1		T6	2		T26	3		T31	4
valid_sources[0x63]	2720	1		T4	1		T26	11		T31	2
valid_sources[0x64]	2442	1		T6	6		T26	2		T31	8
valid_sources[0x65]	2595	1		T4	1		T6	1		T26	7
valid_sources[0x66]	2516	1		T4	1		T12	7		T6	4
valid_sources[0x67]	2903	1		T4	3		T26	10		T31	5
valid_sources[0x68]	2649	1		T4	1		T31	2		T29	2
valid_sources[0x69]	2736	1		T11	2		T26	12		T31	5
valid_sources[0x6a]	2478	1		T4	3		T6	1		T26	9
valid_sources[0x6b]	2401	1		T4	3		T31	1		T29	1
valid_sources[0x6c]	2158	1		T26	3		T29	4		T52	35
valid_sources[0x6d]	2428	1		T26	1		T31	7		T29	2
valid_sources[0x6e]	2435	1		T26	7		T31	2		T29	2
valid_sources[0x6f]	3522	1		T12	7		T26	6		T29	6
valid_sources[0x70]	2774	1		T4	2		T12	1		T11	1
valid_sources[0x71]	2839	1		T6	1		T26	2		T31	2
valid_sources[0x72]	2516	1		T6	1		T26	14		T31	5
valid_sources[0x73]	2932	1		T26	2		T31	2		T29	2
valid_sources[0x74]	2785	1		T6	1		T10	1		T26	11
valid_sources[0x75]	3139	1		T4	1		T6	3		T11	2
valid_sources[0x76]	2728	1		T26	3		T29	3		T52	8
valid_sources[0x77]	2350	1		T4	1		T6	1		T26	3
valid_sources[0x78]	2679	1		T31	6		T29	1		T52	34
valid_sources[0x79]	2444	1		T4	2		T26	8		T31	14
valid_sources[0x7a]	2977	1		T4	1		T6	1		T11	1
valid_sources[0x7b]	2587	1		T11	1		T26	10		T52	49
valid_sources[0x7c]	2433	1		T4	1		T13	1		T26	4
valid_sources[0x7d]	3022	1		T4	2		T11	1		T26	4
valid_sources[0x7e]	2601	1		T4	1		T12	2		T26	1
valid_sources[0x7f]	2340	1		T4	1		T26	6		T31	1
valid_sources[0x80]	2940	1		T6	2		T11	1		T26	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

265561

1

T4

5

T5

6

T12

80

values[0x0]

all_enables

biggest_size

112347

1

T4

17

T5

6

T7

1

values[0x1]

all_enables

biggest_size

112044

1

T4

9

T5

3

T6

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4269	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17892	1		T3	1		T14	1		T17	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8757	1		T30	3		T26	109		T31	6
values[0x0]	6601	1		T1	2		T3	2		T14	8
values[0x1]	6803	1		T1	2		T3	10		T14	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3218	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18943	1		T3	3		T14	1		T17	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55	1		T26	3		T81	5		T69	1
valid_sources[0x01]	66	1		T44	1		T75	7		T68	1
valid_sources[0x02]	58	1		T26	2		T75	2		T57	1
valid_sources[0x03]	67	1		T68	3		T81	5		T69	2
valid_sources[0x04]	60	1		T3	1		T119	1		T30	1
valid_sources[0x05]	94	1		T3	1		T17	1		T22	1
valid_sources[0x06]	78	1		T120	1		T108	1		T121	1
valid_sources[0x07]	66	1		T26	1		T28	1		T67	4
valid_sources[0x08]	79	1		T26	2		T67	3		T75	2
valid_sources[0x09]	68	1		T26	7		T28	2		T80	1
valid_sources[0x0a]	51	1		T3	1		T44	1		T69	4
valid_sources[0x0b]	308	1		T3	1		T26	2		T74	4
valid_sources[0x0c]	77	1		T15	16		T122	3		T26	2
valid_sources[0x0d]	51	1		T18	2		T26	1		T57	1
valid_sources[0x0e]	54	1		T120	1		T28	1		T75	6
valid_sources[0x0f]	50	1		T3	1		T120	2		T26	1
valid_sources[0x10]	88	1		T119	1		T26	1		T28	5
valid_sources[0x11]	80	1		T44	1		T123	11		T75	2
valid_sources[0x12]	82	1		T74	8		T68	1		T81	2
valid_sources[0x13]	82	1		T124	1		T125	1		T68	2
valid_sources[0x14]	70	1		T48	1		T125	3		T26	2
valid_sources[0x15]	107	1		T26	2		T29	7		T28	2
valid_sources[0x16]	74	1		T126	2		T28	3		T66	1
valid_sources[0x17]	59	1		T125	1		T26	2		T72	1
valid_sources[0x18]	78	1		T119	1		T26	12		T75	8
valid_sources[0x19]	49	1		T33	1		T28	1		T66	2
valid_sources[0x1a]	67	1		T3	1		T53	23		T68	1
valid_sources[0x1b]	41	1		T127	1		T67	1		T75	4
valid_sources[0x1c]	190	1		T66	1		T74	4		T75	4
valid_sources[0x1d]	44	1		T75	4		T68	2		T69	1
valid_sources[0x1e]	129	1		T29	28		T75	4		T57	2
valid_sources[0x1f]	79	1		T52	7		T28	1		T67	5
valid_sources[0x20]	74	1		T26	2		T29	5		T28	3
valid_sources[0x21]	127	1		T128	1		T28	1		T75	2
valid_sources[0x22]	61	1		T129	1		T26	10		T69	3
valid_sources[0x23]	69	1		T67	1		T75	2		T68	3
valid_sources[0x24]	61	1		T17	1		T26	3		T67	3
valid_sources[0x25]	135	1		T14	1		T26	5		T29	41
valid_sources[0x26]	95	1		T120	1		T75	6		T68	4
valid_sources[0x27]	84	1		T17	2		T126	1		T29	19
valid_sources[0x28]	79	1		T68	3		T81	2		T69	1
valid_sources[0x29]	73	1		T75	2		T68	2		T81	9
valid_sources[0x2a]	49	1		T130	3		T28	2		T68	2
valid_sources[0x2b]	57	1		T26	1		T28	1		T67	1
valid_sources[0x2c]	86	1		T44	1		T131	3		T66	1
valid_sources[0x2d]	51	1		T26	2		T81	4		T78	1
valid_sources[0x2e]	51	1		T28	1		T75	2		T81	4
valid_sources[0x2f]	55	1		T26	1		T28	2		T75	4
valid_sources[0x30]	58	1		T26	3		T69	1		T71	1
valid_sources[0x31]	82	1		T63	3		T129	1		T28	1
valid_sources[0x32]	51	1		T66	1		T75	4		T68	1
valid_sources[0x33]	109	1		T28	1		T73	17		T68	1
valid_sources[0x34]	54	1		T26	2		T75	6		T81	2
valid_sources[0x35]	63	1		T64	2		T26	1		T75	4
valid_sources[0x36]	79	1		T125	1		T26	2		T74	2
valid_sources[0x37]	53	1		T28	1		T75	2		T57	1
valid_sources[0x38]	124	1		T33	1		T132	16		T29	17
valid_sources[0x39]	120	1		T18	2		T22	1		T44	1
valid_sources[0x3a]	57	1		T130	6		T119	1		T26	2
valid_sources[0x3b]	188	1		T26	3		T66	1		T75	2
valid_sources[0x3c]	54	1		T18	1		T81	2		T69	1
valid_sources[0x3d]	115	1		T31	2		T29	23		T28	1
valid_sources[0x3e]	180	1		T28	1		T74	3		T75	2
valid_sources[0x3f]	132	1		T133	9		T26	3		T28	2
valid_sources[0x40]	73	1		T1	4		T44	2		T26	2
valid_sources[0x41]	77	1		T18	1		T22	1		T26	1
valid_sources[0x42]	76	1		T18	1		T134	1		T74	10
valid_sources[0x43]	97	1		T17	2		T26	3		T27	28
valid_sources[0x44]	102	1		T125	1		T26	1		T66	1
valid_sources[0x45]	53	1		T28	3		T81	3		T69	3
valid_sources[0x46]	59	1		T75	7		T68	1		T81	4
valid_sources[0x47]	63	1		T14	1		T26	1		T28	1
valid_sources[0x48]	81	1		T75	2		T68	1		T81	3
valid_sources[0x49]	71	1		T124	1		T52	2		T74	1
valid_sources[0x4a]	68	1		T108	4		T26	2		T75	2
valid_sources[0x4b]	84	1		T73	20		T68	3		T81	3
valid_sources[0x4c]	48	1		T14	2		T47	1		T57	2
valid_sources[0x4d]	45	1		T74	1		T75	2		T81	1
valid_sources[0x4e]	127	1		T125	1		T66	1		T72	1
valid_sources[0x4f]	73	1		T120	4		T135	2		T26	1
valid_sources[0x50]	98	1		T26	2		T67	3		T74	4
valid_sources[0x51]	67	1		T67	2		T68	5		T81	5
valid_sources[0x52]	59	1		T136	1		T67	1		T75	4
valid_sources[0x53]	273	1		T44	1		T137	3		T138	1
valid_sources[0x54]	95	1		T33	1		T26	1		T67	3
valid_sources[0x55]	57	1		T129	2		T28	4		T66	3
valid_sources[0x56]	42	1		T26	1		T67	2		T75	2
valid_sources[0x57]	105	1		T17	2		T26	12		T72	2
valid_sources[0x58]	70	1		T18	1		T26	1		T29	4
valid_sources[0x59]	49	1		T139	1		T26	1		T28	1
valid_sources[0x5a]	75	1		T31	5		T67	2		T74	3
valid_sources[0x5b]	105	1		T127	1		T26	7		T74	18
valid_sources[0x5c]	254	1		T108	3		T129	1		T27	72
valid_sources[0x5d]	63	1		T64	1		T30	1		T26	1
valid_sources[0x5e]	98	1		T18	2		T26	14		T67	1
valid_sources[0x5f]	74	1		T22	1		T74	2		T75	1
valid_sources[0x60]	73	1		T120	1		T28	1		T81	3
valid_sources[0x61]	35	1		T26	2		T75	2		T81	4
valid_sources[0x62]	84	1		T17	1		T74	1		T75	2
valid_sources[0x63]	96	1		T14	1		T18	1		T26	7
valid_sources[0x64]	67	1		T31	1		T67	3		T74	4
valid_sources[0x65]	84	1		T26	2		T28	1		T75	2
valid_sources[0x66]	96	1		T108	5		T26	3		T75	2
valid_sources[0x67]	107	1		T81	7		T69	2		T140	1
valid_sources[0x68]	94	1		T26	4		T29	5		T28	1
valid_sources[0x69]	94	1		T128	2		T26	2		T27	1
valid_sources[0x6a]	79	1		T45	7		T130	1		T26	1
valid_sources[0x6b]	51	1		T26	1		T28	1		T66	1
valid_sources[0x6c]	109	1		T33	1		T120	1		T26	1
valid_sources[0x6d]	89	1		T135	1		T66	1		T68	3
valid_sources[0x6e]	88	1		T18	2		T26	1		T29	8
valid_sources[0x6f]	97	1		T27	23		T28	2		T75	7
valid_sources[0x70]	51	1		T28	1		T75	4		T80	1
valid_sources[0x71]	47	1		T28	1		T69	2		T140	1
valid_sources[0x72]	68	1		T26	1		T31	2		T28	1
valid_sources[0x73]	442	1		T18	1		T26	5		T28	1
valid_sources[0x74]	85	1		T46	13		T26	3		T75	8
valid_sources[0x75]	77	1		T125	3		T26	1		T28	1
valid_sources[0x76]	62	1		T120	1		T28	2		T75	2
valid_sources[0x77]	87	1		T28	3		T72	1		T73	11
valid_sources[0x78]	127	1		T135	2		T75	2		T81	3
valid_sources[0x79]	93	1		T127	1		T128	1		T29	4
valid_sources[0x7a]	48	1		T26	1		T81	2		T69	2
valid_sources[0x7b]	76	1		T141	13		T28	1		T75	2
valid_sources[0x7c]	42	1		T28	2		T75	4		T68	1
valid_sources[0x7d]	84	1		T26	2		T66	1		T67	2
valid_sources[0x7e]	77	1		T33	1		T28	1		T75	2
valid_sources[0x7f]	110	1		T20	14		T127	1		T134	5
valid_sources[0x80]	60	1		T30	1		T28	1		T68	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6147

1

T30

1

T26

102

T31

3

values[0x0]

all_enables

biggest_size

5923

1

T3

1

T14

1

T17

2

values[0x1]

all_enables

biggest_size

5822

1

T18

1

T51

2

T25

1