Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	216451	1		T4	74		T5	34		T7	4
full_word	491439	1		T4	31		T5	15		T12	80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	707580	1		T4	105		T5	49		T12	80
auto[TlIntgErrCmd]	95	1		T66	2		T67	5		T71	6
auto[TlIntgErrData]	119	1		T66	6		T67	11		T71	2
auto[TlIntgErrBoth]	96	1		T66	2		T67	4		T71	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	439937	1		T4	10		T5	18		T12	80
auto[1]	267953	1		T4	95		T5	31		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	174038	1		T4	5		T5	12		T7	4
auto[TlIntgErrNone]	partial	auto[1]	42127	1		T4	69		T5	22		T6	67
auto[TlIntgErrNone]	full_word	auto[0]	265740	1		T4	5		T5	6		T12	80
auto[TlIntgErrNone]	full_word	auto[1]	225675	1		T4	26		T5	9		T7	1
auto[TlIntgErrCmd]	partial	auto[0]	51	1		T66	1		T67	3		T71	2
auto[TlIntgErrCmd]	partial	auto[1]	35	1		T66	1		T67	2		T71	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T71	1		T107	2		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T106	1		T107	1		T103	2
auto[TlIntgErrData]	partial	auto[0]	63	1		T66	4		T67	4		T71	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T66	1		T67	7		T71	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T112	1		T111	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T66	1		T106	2		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T66	2		T67	2		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T67	2		T71	2		T114	2
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T106	1		T115	1		T107	1