Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.57	100.00	55.32	85.05		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	37952608	11682	0	0
late_debug_enable_rd_A	37952608	1668	0	0
late_debug_enable_regwen_rd_A	37952608	1104	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37952608	11682	0	0
T26	162182	284	0	0
T27	52587	124	0	0
T28	199877	42	0	0
T29	7163	390	0	0
T53	310077	119	0	0
T66	52521	1	0	0
T67	109593	8	0	0
T68	99109	147	0	0
T69	21412	697	0	0
T70	16495	42	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37952608	1668	0	0
T28	199877	31	0	0
T57	40549	30	0	0
T66	52521	34	0	0
T72	9521	8	0	0
T77	5632	2	0	0
T80	10982	12	0	0
T83	246381	125	0	0
T85	20502	30	0	0
T106	50257	22	0	0
T107	79979	101	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37952608	1104	0	0
T28	199877	6	0	0
T57	40549	34	0	0
T66	52521	36	0	0
T72	9521	11	0	0
T77	5632	1	0	0
T80	10982	3	0	0
T83	246381	128	0	0
T85	20502	29	0	0
T106	50257	38	0	0
T107	79979	101	0	0