Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T10
11CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10699774 10699078 0 0
selKnown1 12286631 12285935 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10699774 10699078 0 0
T1 358 356 0 0
T2 3812 3808 0 0
T3 312 308 0 0
T4 0 12 0 0
T5 0 23 0 0
T6 0 17 0 0
T9 0 9 0 0
T10 0 7 0 0
T14 330 326 0 0
T17 370 366 0 0
T18 318 314 0 0
T19 4052 4048 0 0
T20 312 308 0 0
T21 308 304 0 0
T22 388 384 0 0
T23 0 20 0 0
T49 0 40 0 0
T50 0 20 0 0
T51 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 12286631 12285935 0 0
T1 1313 1311 0 0
T2 10013 10009 0 0
T3 2250 2246 0 0
T4 0 12 0 0
T5 0 8 0 0
T6 0 6 0 0
T9 0 8 0 0
T10 0 8 0 0
T14 1764 1760 0 0
T17 2480 2476 0 0
T18 2252 2248 0 0
T19 10173 10169 0 0
T20 1530 1526 0 0
T21 1039 1035 0 0
T22 1613 1609 0 0
T23 0 20 0 0
T49 0 40 0 0
T50 0 20 0 0
T51 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T10
11CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 560999 560928 0 0
selKnown1 2147964 2147893 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 560999 560928 0 0
T1 179 178 0 0
T2 1895 1894 0 0
T3 155 154 0 0
T14 164 163 0 0
T17 184 183 0 0
T18 158 157 0 0
T19 2015 2014 0 0
T20 155 154 0 0
T21 153 152 0 0
T22 193 192 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147964 2147893 0 0
T1 1134 1133 0 0
T2 8096 8095 0 0
T3 2093 2092 0 0
T14 1598 1597 0 0
T17 2294 2293 0 0
T18 2092 2091 0 0
T19 8136 8135 0 0
T20 1373 1372 0 0
T21 884 883 0 0
T22 1418 1417 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T10
11CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 167 96 0 0
selKnown1 169 98 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 167 96 0 0
T2 11 10 0 0
T3 1 0 0 0
T4 0 6 0 0
T5 0 4 0 0
T6 0 3 0 0
T9 0 4 0 0
T10 0 3 0 0
T14 1 0 0 0
T17 1 0 0 0
T18 1 0 0 0
T19 11 10 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 10 0 0
T49 0 20 0 0
T50 0 10 0 0
T51 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 169 98 0 0
T2 11 10 0 0
T3 1 0 0 0
T4 0 6 0 0
T5 0 4 0 0
T6 0 3 0 0
T9 0 4 0 0
T10 0 4 0 0
T14 1 0 0 0
T17 1 0 0 0
T18 1 0 0 0
T19 11 10 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 10 0 0
T49 0 20 0 0
T50 0 10 0 0
T51 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T10
11CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10137131 10136854 0 0
selKnown1 10137131 10136854 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10137131 10136854 0 0
T1 179 178 0 0
T2 1895 1894 0 0
T3 155 154 0 0
T14 164 163 0 0
T17 184 183 0 0
T18 158 157 0 0
T19 2015 2014 0 0
T20 155 154 0 0
T21 153 152 0 0
T22 193 192 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10137131 10136854 0 0
T1 179 178 0 0
T2 1895 1894 0 0
T3 155 154 0 0
T14 164 163 0 0
T17 184 183 0 0
T18 158 157 0 0
T19 2015 2014 0 0
T20 155 154 0 0
T21 153 152 0 0
T22 193 192 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T10
11CoveredT5,T6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1477 1200 0 0
selKnown1 1367 1090 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1477 1200 0 0
T2 11 10 0 0
T3 1 0 0 0
T4 0 6 0 0
T5 0 19 0 0
T6 0 14 0 0
T9 0 5 0 0
T10 0 4 0 0
T14 1 0 0 0
T17 1 0 0 0
T18 1 0 0 0
T19 11 10 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 10 0 0
T49 0 20 0 0
T50 0 10 0 0
T51 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1367 1090 0 0
T2 11 10 0 0
T3 1 0 0 0
T4 0 6 0 0
T5 0 4 0 0
T6 0 3 0 0
T9 0 4 0 0
T10 0 4 0 0
T14 1 0 0 0
T17 1 0 0 0
T18 1 0 0 0
T19 11 10 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 10 0 0
T49 0 20 0 0
T50 0 10 0 0
T51 1 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%