Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	58.46			58.46
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.46			58.46

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.46			58.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T3,*T17,*T20	Yes	T3,T14,T17	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T3,T14	Yes	T3,T14,T17	INPUT
data_o[56:0]	Yes	Yes	T3,T17,T20	Yes	T3,T14,T17	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T17,T25	Yes	T3,T14,T17	OUTPUT
err_o[1:0]	Yes	Yes	T3,T17,T21	Yes	T3,T17,T20	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	152	58.46
Total Bits 0->1	130	76	58.46
Total Bits 1->0	130	76	58.46

Ports	4	2	50.00
Port Bits	260	152	58.46
Port Bits 0->1	130	76	58.46
Port Bits 1->0	130	76	58.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T20,*T33,T9	Yes	T9,T24,T52	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T9,T24,T53	Yes	T20,T33,T9	INPUT
data_o[4:0]	Yes	Yes	*T20,*T33,*T9	Yes	T9,T24,T52	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[56:6]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
syndrome_o[6:0]	Yes	Yes	T9,T24,T57	Yes	T44,T9,T13	OUTPUT
err_o[1:0]	Yes	Yes	T9,T24,T52	Yes	T20,T9,T45	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T3,*T17,*T25	Yes	T3,T17,T25	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T3,T14	Yes	T3,T14,T17	INPUT
data_o[56:0]	Yes	Yes	T3,T17,T25	Yes	T3,T17,T25	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T17,T25	Yes	T3,T17,T25	OUTPUT
err_o[1:0]	Yes	Yes	T3,T17,T25	Yes	T3,T17,T25	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T4,*T9,*T5	Yes	T14,T18,T4	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T4,T9,T5	Yes	T14,T18,T4	INPUT
data_o[56:0]	Yes	Yes	T4,T9,T5	Yes	T14,T18,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T9,T5,T13	Yes	T14,T18,T15	OUTPUT
err_o[1:0]	Yes	Yes	T21,T4,T15	Yes	T4,T9,T5	OUTPUT

*Tests covering at least one bit in the range