Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	208778	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	588766	1		T5	80		T13	80		T6	24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	487338	1		T5	80		T13	80		T6	12
values[0x0]	152939	1		T6	25		T9	19		T10	38
values[0x1]	157267	1		T6	37		T9	29		T10	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160289	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	637255	1		T5	80		T13	80		T6	36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2646	1		T31	1		T28	22		T30	8
valid_sources[0x01]	3758	1		T31	1		T28	18		T29	293
valid_sources[0x02]	3259	1		T31	1		T28	26		T29	40
valid_sources[0x03]	3880	1		T31	3		T28	16		T29	8
valid_sources[0x04]	3215	1		T21	1		T31	4		T28	21
valid_sources[0x05]	3295	1		T31	1		T28	22		T29	17
valid_sources[0x06]	3114	1		T31	2		T28	21		T29	23
valid_sources[0x07]	2741	1		T28	28		T29	24		T30	3
valid_sources[0x08]	3267	1		T5	1		T31	2		T28	26
valid_sources[0x09]	3204	1		T5	1		T28	21		T72	2
valid_sources[0x0a]	3430	1		T31	2		T28	20		T30	2
valid_sources[0x0b]	2785	1		T13	11		T9	3		T28	19
valid_sources[0x0c]	3434	1		T5	2		T7	2		T31	5
valid_sources[0x0d]	3325	1		T28	17		T29	8		T30	1
valid_sources[0x0e]	2803	1		T5	1		T31	5		T28	28
valid_sources[0x0f]	3691	1		T9	2		T15	9		T31	4
valid_sources[0x10]	2978	1		T13	19		T28	18		T29	13
valid_sources[0x11]	2961	1		T5	2		T11	1		T31	1
valid_sources[0x12]	3395	1		T31	1		T28	16		T30	3
valid_sources[0x13]	2752	1		T5	2		T9	1		T31	8
valid_sources[0x14]	3627	1		T5	1		T31	2		T28	19
valid_sources[0x15]	3509	1		T5	2		T28	27		T30	6
valid_sources[0x16]	2909	1		T31	2		T28	18		T29	11
valid_sources[0x17]	2819	1		T31	2		T28	15		T30	2
valid_sources[0x18]	3212	1		T21	4		T31	3		T28	25
valid_sources[0x19]	3576	1		T31	1		T28	25		T30	5
valid_sources[0x1a]	2633	1		T31	1		T28	17		T29	14
valid_sources[0x1b]	2828	1		T31	1		T28	24		T29	56
valid_sources[0x1c]	2498	1		T28	20		T29	9		T30	3
valid_sources[0x1d]	3022	1		T31	2		T28	21		T29	10
valid_sources[0x1e]	3478	1		T31	1		T28	21		T29	13
valid_sources[0x1f]	3127	1		T5	1		T9	1		T31	4
valid_sources[0x20]	3053	1		T5	1		T28	24		T29	12
valid_sources[0x21]	2720	1		T11	3		T31	1		T28	19
valid_sources[0x22]	2807	1		T31	2		T28	21		T30	2
valid_sources[0x23]	3272	1		T9	1		T31	4		T28	26
valid_sources[0x24]	2882	1		T5	1		T9	1		T31	3
valid_sources[0x25]	2946	1		T5	1		T31	2		T28	31
valid_sources[0x26]	2734	1		T31	1		T28	25		T29	10
valid_sources[0x27]	2328	1		T31	1		T28	25		T29	4
valid_sources[0x28]	2797	1		T7	2		T31	4		T28	20
valid_sources[0x29]	3509	1		T11	4		T28	28		T29	5
valid_sources[0x2a]	2894	1		T28	20		T29	49		T30	6
valid_sources[0x2b]	3014	1		T9	1		T21	1		T31	2
valid_sources[0x2c]	2356	1		T31	1		T28	33		T29	2
valid_sources[0x2d]	2771	1		T5	2		T9	1		T31	1
valid_sources[0x2e]	2943	1		T31	3		T28	18		T29	8
valid_sources[0x2f]	2960	1		T5	1		T31	8		T28	15
valid_sources[0x30]	2851	1		T5	1		T31	4		T28	22
valid_sources[0x31]	3402	1		T5	1		T21	4		T28	16
valid_sources[0x32]	3415	1		T11	1		T31	1		T28	13
valid_sources[0x33]	2849	1		T5	1		T31	1		T28	29
valid_sources[0x34]	2853	1		T11	3		T31	4		T28	20
valid_sources[0x35]	3244	1		T9	2		T11	2		T31	1
valid_sources[0x36]	2778	1		T5	1		T9	1		T31	3
valid_sources[0x37]	2924	1		T5	1		T13	10		T31	6
valid_sources[0x38]	3459	1		T28	26		T29	35		T30	3
valid_sources[0x39]	3146	1		T9	1		T31	2		T28	25
valid_sources[0x3a]	3355	1		T11	7		T31	2		T28	18
valid_sources[0x3b]	3828	1		T28	24		T30	3		T72	3
valid_sources[0x3c]	2865	1		T31	5		T28	14		T29	15
valid_sources[0x3d]	2934	1		T11	1		T31	5		T28	22
valid_sources[0x3e]	3242	1		T9	1		T31	1		T28	30
valid_sources[0x3f]	3724	1		T5	1		T11	2		T31	3
valid_sources[0x40]	3033	1		T5	1		T9	1		T21	2
valid_sources[0x41]	3169	1		T5	1		T6	74		T31	1
valid_sources[0x42]	3367	1		T9	1		T31	4		T28	25
valid_sources[0x43]	3262	1		T31	1		T28	18		T29	1
valid_sources[0x44]	2851	1		T11	7		T31	1		T28	31
valid_sources[0x45]	3518	1		T28	20		T29	22		T30	7
valid_sources[0x46]	3065	1		T5	1		T21	1		T11	3
valid_sources[0x47]	3450	1		T31	2		T28	11		T29	10
valid_sources[0x48]	2657	1		T11	1		T31	2		T28	23
valid_sources[0x49]	3044	1		T5	1		T9	1		T31	2
valid_sources[0x4a]	2483	1		T11	2		T28	14		T30	1
valid_sources[0x4b]	3102	1		T9	1		T31	2		T28	20
valid_sources[0x4c]	3561	1		T9	1		T31	3		T28	29
valid_sources[0x4d]	2805	1		T31	3		T28	16		T30	1
valid_sources[0x4e]	2860	1		T5	1		T31	2		T28	15
valid_sources[0x4f]	3177	1		T13	1		T31	5		T28	18
valid_sources[0x50]	2950	1		T7	1		T31	2		T28	23
valid_sources[0x51]	2984	1		T9	2		T31	3		T28	19
valid_sources[0x52]	3088	1		T5	1		T9	1		T31	4
valid_sources[0x53]	2759	1		T9	1		T28	24		T29	20
valid_sources[0x54]	2821	1		T31	1		T28	22		T30	2
valid_sources[0x55]	3481	1		T9	1		T31	2		T28	22
valid_sources[0x56]	3894	1		T28	12		T29	30		T30	5
valid_sources[0x57]	2796	1		T13	10		T9	1		T31	4
valid_sources[0x58]	3547	1		T31	7		T28	31		T29	17
valid_sources[0x59]	2697	1		T31	1		T28	21		T30	4
valid_sources[0x5a]	3290	1		T9	1		T31	3		T28	22
valid_sources[0x5b]	3414	1		T21	1		T11	6		T31	2
valid_sources[0x5c]	2702	1		T5	1		T31	5		T28	24
valid_sources[0x5d]	3025	1		T21	2		T31	2		T28	20
valid_sources[0x5e]	3218	1		T9	1		T26	71		T31	6
valid_sources[0x5f]	2644	1		T5	1		T31	5		T28	14
valid_sources[0x60]	2910	1		T5	2		T31	3		T28	20
valid_sources[0x61]	2902	1		T9	1		T31	1		T28	26
valid_sources[0x62]	3269	1		T5	3		T31	3		T28	20
valid_sources[0x63]	2800	1		T28	30		T30	6		T72	3
valid_sources[0x64]	2756	1		T9	1		T28	17		T29	2
valid_sources[0x65]	2497	1		T31	5		T28	19		T29	9
valid_sources[0x66]	2846	1		T5	1		T28	15		T29	6
valid_sources[0x67]	2686	1		T31	1		T28	23		T30	5
valid_sources[0x68]	3161	1		T13	6		T21	1		T11	1
valid_sources[0x69]	3305	1		T31	3		T28	23		T30	4
valid_sources[0x6a]	3031	1		T31	1		T28	24		T29	18
valid_sources[0x6b]	3139	1		T9	1		T31	2		T28	19
valid_sources[0x6c]	3820	1		T5	1		T31	2		T28	17
valid_sources[0x6d]	2829	1		T31	3		T28	21		T29	36
valid_sources[0x6e]	2801	1		T9	1		T28	25		T29	2
valid_sources[0x6f]	3280	1		T9	2		T31	1		T28	17
valid_sources[0x70]	3572	1		T31	1		T28	14		T30	3
valid_sources[0x71]	2747	1		T28	23		T29	33		T30	4
valid_sources[0x72]	3345	1		T31	2		T28	18		T30	5
valid_sources[0x73]	3840	1		T11	3		T31	3		T28	27
valid_sources[0x74]	3044	1		T9	1		T11	3		T31	2
valid_sources[0x75]	2828	1		T31	1		T28	25		T30	10
valid_sources[0x76]	3134	1		T21	7		T11	1		T31	4
valid_sources[0x77]	3362	1		T5	1		T31	1		T28	25
valid_sources[0x78]	5162	1		T5	1		T31	7		T28	28
valid_sources[0x79]	2965	1		T5	1		T31	1		T28	28
valid_sources[0x7a]	3506	1		T31	2		T28	25		T29	115
valid_sources[0x7b]	2504	1		T5	2		T31	1		T28	15
valid_sources[0x7c]	3296	1		T9	1		T11	1		T28	14
valid_sources[0x7d]	3141	1		T31	2		T28	24		T29	1
valid_sources[0x7e]	3157	1		T5	1		T9	1		T31	2
valid_sources[0x7f]	3089	1		T28	19		T29	15		T30	2
valid_sources[0x80]	3162	1		T21	1		T28	18		T30	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

287614

1

T5

80

T13

80

T6

9

values[0x0]

all_enables

biggest_size

151117

1

T6

6

T9

8

T10

31

values[0x1]

all_enables

biggest_size

150035

1

T6

9

T9

10

T10

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5153	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21521	1		T1	4		T3	3		T4	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10223	1		T31	79		T28	33		T29	32
values[0x0]	8082	1		T1	4		T2	7		T3	4
values[0x1]	8369	1		T1	4		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4001	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22673	1		T1	5		T3	3		T4	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63	1		T118	1		T31	2		T67	1
valid_sources[0x01]	102	1		T67	1		T71	3		T75	4
valid_sources[0x02]	100	1		T119	1		T72	1		T67	2
valid_sources[0x03]	87	1		T2	1		T120	1		T67	2
valid_sources[0x04]	98	1		T31	2		T66	1		T67	1
valid_sources[0x05]	91	1		T119	2		T28	1		T70	2
valid_sources[0x06]	82	1		T121	2		T31	2		T67	1
valid_sources[0x07]	61	1		T122	1		T67	2		T83	3
valid_sources[0x08]	78	1		T28	3		T70	1		T75	2
valid_sources[0x09]	80	1		T3	1		T31	4		T72	1
valid_sources[0x0a]	102	1		T123	2		T31	1		T29	1
valid_sources[0x0b]	78	1		T14	2		T31	2		T67	2
valid_sources[0x0c]	75	1		T124	4		T31	3		T66	1
valid_sources[0x0d]	76	1		T43	1		T31	5		T29	1
valid_sources[0x0e]	107	1		T120	1		T125	13		T126	1
valid_sources[0x0f]	73	1		T31	1		T66	1		T75	7
valid_sources[0x10]	196	1		T122	1		T29	1		T30	3
valid_sources[0x11]	75	1		T67	4		T70	1		T83	2
valid_sources[0x12]	64	1		T123	1		T127	1		T66	1
valid_sources[0x13]	63	1		T128	1		T118	1		T31	2
valid_sources[0x14]	104	1		T31	4		T29	1		T67	2
valid_sources[0x15]	93	1		T49	1		T129	2		T130	1
valid_sources[0x16]	85	1		T119	1		T131	1		T30	1
valid_sources[0x17]	100	1		T31	4		T29	1		T82	1
valid_sources[0x18]	120	1		T132	2		T60	2		T126	1
valid_sources[0x19]	105	1		T31	3		T28	2		T66	1
valid_sources[0x1a]	284	1		T4	1		T31	1		T29	2
valid_sources[0x1b]	102	1		T132	1		T30	1		T83	3
valid_sources[0x1c]	66	1		T132	1		T31	2		T69	1
valid_sources[0x1d]	106	1		T28	1		T67	1		T70	1
valid_sources[0x1e]	133	1		T133	7		T75	3		T83	2
valid_sources[0x1f]	73	1		T17	3		T31	1		T70	3
valid_sources[0x20]	88	1		T121	1		T30	3		T69	2
valid_sources[0x21]	187	1		T31	2		T66	1		T67	1
valid_sources[0x22]	86	1		T43	2		T132	1		T67	1
valid_sources[0x23]	110	1		T31	6		T29	1		T73	2
valid_sources[0x24]	105	1		T124	2		T31	1		T70	1
valid_sources[0x25]	91	1		T27	1		T31	6		T29	1
valid_sources[0x26]	70	1		T124	4		T31	1		T29	2
valid_sources[0x27]	111	1		T121	1		T28	3		T67	2
valid_sources[0x28]	157	1		T133	1		T31	1		T68	59
valid_sources[0x29]	105	1		T122	2		T119	2		T31	4
valid_sources[0x2a]	74	1		T118	1		T66	1		T70	2
valid_sources[0x2b]	92	1		T50	7		T119	1		T67	1
valid_sources[0x2c]	96	1		T28	3		T66	1		T70	1
valid_sources[0x2d]	95	1		T27	1		T44	5		T31	3
valid_sources[0x2e]	84	1		T132	1		T66	1		T69	2
valid_sources[0x2f]	92	1		T27	1		T50	1		T75	1
valid_sources[0x30]	98	1		T67	2		T75	5		T63	4
valid_sources[0x31]	93	1		T29	1		T75	1		T62	1
valid_sources[0x32]	81	1		T42	2		T120	1		T31	5
valid_sources[0x33]	83	1		T126	1		T66	1		T67	1
valid_sources[0x34]	101	1		T120	2		T134	11		T31	2
valid_sources[0x35]	296	1		T72	1		T73	7		T67	2
valid_sources[0x36]	126	1		T31	2		T28	3		T67	1
valid_sources[0x37]	118	1		T27	1		T31	1		T75	2
valid_sources[0x38]	124	1		T31	2		T30	1		T67	1
valid_sources[0x39]	80	1		T122	1		T135	1		T31	1
valid_sources[0x3a]	144	1		T31	1		T30	1		T71	3
valid_sources[0x3b]	101	1		T31	1		T75	1		T83	7
valid_sources[0x3c]	91	1		T4	3		T122	4		T120	1
valid_sources[0x3d]	55	1		T31	1		T70	4		T83	1
valid_sources[0x3e]	161	1		T28	3		T29	1		T70	1
valid_sources[0x3f]	75	1		T27	1		T118	1		T31	1
valid_sources[0x40]	112	1		T50	1		T136	9		T83	4
valid_sources[0x41]	120	1		T128	1		T31	1		T28	6
valid_sources[0x42]	101	1		T31	5		T71	1		T75	4
valid_sources[0x43]	68	1		T31	2		T30	1		T69	4
valid_sources[0x44]	98	1		T31	2		T29	3		T70	1
valid_sources[0x45]	81	1		T14	4		T119	1		T60	1
valid_sources[0x46]	99	1		T49	1		T29	2		T30	1
valid_sources[0x47]	76	1		T31	2		T67	2		T68	5
valid_sources[0x48]	59	1		T31	2		T28	2		T75	3
valid_sources[0x49]	115	1		T137	1		T138	1		T30	2
valid_sources[0x4a]	77	1		T31	1		T66	1		T67	1
valid_sources[0x4b]	90	1		T31	7		T29	1		T30	2
valid_sources[0x4c]	143	1		T31	2		T67	2		T83	2
valid_sources[0x4d]	57	1		T75	1		T62	3		T82	1
valid_sources[0x4e]	91	1		T31	2		T67	2		T70	1
valid_sources[0x4f]	97	1		T133	1		T31	1		T66	1
valid_sources[0x50]	61	1		T70	1		T82	1		T83	4
valid_sources[0x51]	80	1		T49	1		T67	1		T75	1
valid_sources[0x52]	80	1		T138	2		T31	4		T67	1
valid_sources[0x53]	105	1		T43	1		T31	1		T30	1
valid_sources[0x54]	106	1		T124	1		T70	4		T83	1
valid_sources[0x55]	76	1		T139	3		T31	1		T28	1
valid_sources[0x56]	94	1		T51	1		T122	2		T31	2
valid_sources[0x57]	111	1		T31	4		T67	1		T69	1
valid_sources[0x58]	74	1		T31	1		T82	6		T83	3
valid_sources[0x59]	87	1		T31	2		T30	1		T69	2
valid_sources[0x5a]	85	1		T137	3		T31	2		T28	6
valid_sources[0x5b]	57	1		T31	3		T67	2		T83	3
valid_sources[0x5c]	63	1		T45	1		T67	2		T75	1
valid_sources[0x5d]	87	1		T4	1		T49	4		T67	2
valid_sources[0x5e]	107	1		T2	1		T27	1		T119	1
valid_sources[0x5f]	120	1		T31	2		T30	1		T71	2
valid_sources[0x60]	97	1		T2	1		T67	2		T75	4
valid_sources[0x61]	63	1		T31	1		T70	2		T75	2
valid_sources[0x62]	90	1		T29	1		T67	1		T70	4
valid_sources[0x63]	75	1		T2	1		T70	1		T75	1
valid_sources[0x64]	87	1		T72	1		T82	4		T83	4
valid_sources[0x65]	72	1		T140	1		T31	1		T67	2
valid_sources[0x66]	104	1		T119	1		T67	2		T74	1
valid_sources[0x67]	92	1		T120	2		T31	1		T70	2
valid_sources[0x68]	108	1		T31	1		T29	1		T67	1
valid_sources[0x69]	91	1		T27	1		T31	2		T66	1
valid_sources[0x6a]	99	1		T128	1		T130	1		T138	3
valid_sources[0x6b]	62	1		T31	1		T67	2		T70	1
valid_sources[0x6c]	106	1		T119	1		T31	2		T70	2
valid_sources[0x6d]	113	1		T121	1		T122	5		T119	1
valid_sources[0x6e]	101	1		T3	1		T31	5		T29	1
valid_sources[0x6f]	67	1		T66	1		T70	1		T75	1
valid_sources[0x70]	81	1		T49	1		T67	3		T75	1
valid_sources[0x71]	103	1		T141	1		T31	1		T67	2
valid_sources[0x72]	95	1		T141	1		T31	1		T66	1
valid_sources[0x73]	881	1		T14	2		T124	2		T28	2
valid_sources[0x74]	69	1		T67	1		T83	1		T63	2
valid_sources[0x75]	93	1		T29	1		T68	3		T70	2
valid_sources[0x76]	76	1		T31	4		T29	2		T71	3
valid_sources[0x77]	102	1		T31	2		T30	3		T67	1
valid_sources[0x78]	141	1		T31	2		T30	6		T70	2
valid_sources[0x79]	127	1		T119	1		T138	2		T66	1
valid_sources[0x7a]	84	1		T31	1		T71	5		T74	1
valid_sources[0x7b]	97	1		T27	1		T127	2		T131	2
valid_sources[0x7c]	105	1		T41	3		T31	1		T30	5
valid_sources[0x7d]	99	1		T73	2		T67	1		T71	1
valid_sources[0x7e]	79	1		T2	1		T139	5		T132	4
valid_sources[0x7f]	129	1		T31	1		T69	13		T70	1
valid_sources[0x80]	79	1		T120	1		T31	2		T75	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7206

1

T31

71

T28

12

T29

13

values[0x0]

all_enables

biggest_size

7233

1

T1

3

T3

1

T4

2

values[0x1]

all_enables

biggest_size

7082

1

T1

1

T3

2

T4

2