Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	251930	1		T6	50		T9	41		T10	38
full_word	590609	1		T5	80		T13	80		T6	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	842249	1		T5	80		T13	80		T6	74
auto[TlIntgErrCmd]	94	1		T28	4		T29	6		T71	6
auto[TlIntgErrData]	96	1		T28	2		T29	3		T71	5
auto[TlIntgErrBoth]	100	1		T28	4		T29	1		T71	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	489592	1		T5	80		T13	80		T6	12
auto[1]	352947	1		T6	62		T9	48		T10	62

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	201613	1		T6	3		T9	11		T10	24
auto[TlIntgErrNone]	partial	auto[1]	50050	1		T6	47		T9	30		T10	14
auto[TlIntgErrNone]	full_word	auto[0]	287856	1		T5	80		T13	80		T6	9
auto[TlIntgErrNone]	full_word	auto[1]	302730	1		T6	15		T9	18		T10	48
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T28	2		T71	1		T55	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T28	2		T29	5		T71	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T29	1		T71	1		T110	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T108	1		T110	1		T111	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T28	2		T29	1		T71	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T29	2		T71	2		T55	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T71	1		T104	1		T112	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T113	2		T114	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T71	2		T55	2		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T28	4		T29	1		T71	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T55	1		T106	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T71	1		T116	1		T110	1