SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1731033 | 1718827 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |