Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	230292	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	590093	1		T2	2		T4	42		T5	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	538419	1		T2	8		T4	20		T6	18
values[0x0]	138834	1		T4	39		T5	22		T6	34
values[0x1]	143132	1		T2	1		T4	24		T5	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173977	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	646408	1		T2	7		T4	44		T5	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3590	1		T9	2		T8	2		T10	1
valid_sources[0x01]	3240	1		T2	3		T6	1		T9	1
valid_sources[0x02]	3487	1		T6	2		T10	1		T31	2
valid_sources[0x03]	3044	1		T32	4		T33	24		T30	12
valid_sources[0x04]	3581	1		T32	3		T33	25		T29	6
valid_sources[0x05]	2652	1		T32	1		T33	24		T30	13
valid_sources[0x06]	3645	1		T31	2		T32	5		T33	23
valid_sources[0x07]	3525	1		T5	1		T8	2		T11	2
valid_sources[0x08]	3888	1		T11	2		T31	4		T32	1
valid_sources[0x09]	3718	1		T10	1		T11	2		T31	4
valid_sources[0x0a]	2959	1		T8	3		T31	3		T32	5
valid_sources[0x0b]	3096	1		T31	3		T33	26		T87	4
valid_sources[0x0c]	3056	1		T31	2		T32	2		T33	31
valid_sources[0x0d]	3077	1		T8	1		T10	3		T33	20
valid_sources[0x0e]	2987	1		T31	1		T32	5		T33	14
valid_sources[0x0f]	2760	1		T4	3		T31	3		T32	3
valid_sources[0x10]	2513	1		T10	1		T31	5		T32	5
valid_sources[0x11]	3350	1		T11	1		T31	1		T32	1
valid_sources[0x12]	3129	1		T32	2		T33	23		T86	3
valid_sources[0x13]	3186	1		T4	3		T6	2		T31	2
valid_sources[0x14]	3516	1		T5	1		T32	1		T33	25
valid_sources[0x15]	3807	1		T8	1		T10	1		T33	36
valid_sources[0x16]	3797	1		T6	1		T11	1		T32	1
valid_sources[0x17]	2709	1		T8	1		T31	4		T33	21
valid_sources[0x18]	3299	1		T31	1		T33	23		T34	5
valid_sources[0x19]	2847	1		T8	1		T10	1		T31	1
valid_sources[0x1a]	3404	1		T10	1		T11	1		T31	1
valid_sources[0x1b]	3669	1		T8	1		T31	4		T32	5
valid_sources[0x1c]	2967	1		T13	9		T31	2		T33	29
valid_sources[0x1d]	3100	1		T4	3		T31	2		T32	2
valid_sources[0x1e]	2905	1		T4	1		T5	1		T10	1
valid_sources[0x1f]	5320	1		T31	2		T32	4		T33	26
valid_sources[0x20]	2814	1		T31	5		T32	1		T33	28
valid_sources[0x21]	3404	1		T8	1		T31	1		T32	2
valid_sources[0x22]	3018	1		T2	1		T31	2		T32	4
valid_sources[0x23]	3261	1		T31	1		T32	2		T33	21
valid_sources[0x24]	3299	1		T6	1		T31	2		T32	4
valid_sources[0x25]	3589	1		T32	3		T33	18		T29	27
valid_sources[0x26]	2592	1		T9	1		T11	1		T31	1
valid_sources[0x27]	3027	1		T6	2		T8	1		T31	1
valid_sources[0x28]	2736	1		T5	1		T31	2		T32	3
valid_sources[0x29]	2691	1		T6	1		T8	1		T11	2
valid_sources[0x2a]	3269	1		T5	2		T31	1		T32	3
valid_sources[0x2b]	2855	1		T31	1		T33	13		T86	1
valid_sources[0x2c]	3334	1		T9	1		T31	4		T32	1
valid_sources[0x2d]	2670	1		T10	3		T31	1		T33	24
valid_sources[0x2e]	3588	1		T6	1		T31	1		T32	2
valid_sources[0x2f]	3320	1		T2	1		T5	1		T31	2
valid_sources[0x30]	3356	1		T32	1		T33	16		T34	2
valid_sources[0x31]	3563	1		T31	1		T32	2		T33	29
valid_sources[0x32]	3627	1		T31	2		T32	2		T33	16
valid_sources[0x33]	3777	1		T6	2		T8	1		T31	2
valid_sources[0x34]	4470	1		T6	1		T31	2		T32	3
valid_sources[0x35]	3146	1		T6	2		T8	2		T31	1
valid_sources[0x36]	3815	1		T11	2		T31	1		T32	3
valid_sources[0x37]	2913	1		T6	1		T8	1		T31	3
valid_sources[0x38]	2775	1		T31	5		T32	1		T33	17
valid_sources[0x39]	2529	1		T6	2		T8	1		T31	4
valid_sources[0x3a]	3344	1		T31	3		T32	1		T33	20
valid_sources[0x3b]	3009	1		T6	1		T31	3		T33	32
valid_sources[0x3c]	3039	1		T31	3		T32	4		T33	16
valid_sources[0x3d]	2964	1		T4	30		T6	1		T31	4
valid_sources[0x3e]	2997	1		T6	1		T11	1		T33	27
valid_sources[0x3f]	2980	1		T6	1		T11	1		T31	2
valid_sources[0x40]	3020	1		T10	2		T31	3		T32	2
valid_sources[0x41]	2670	1		T8	1		T11	1		T31	1
valid_sources[0x42]	3022	1		T8	2		T31	1		T32	4
valid_sources[0x43]	2913	1		T10	2		T31	1		T32	2
valid_sources[0x44]	3035	1		T8	1		T33	20		T34	3
valid_sources[0x45]	3462	1		T4	1		T10	1		T31	2
valid_sources[0x46]	4093	1		T6	1		T9	5		T11	7
valid_sources[0x47]	3742	1		T31	3		T32	2		T33	32
valid_sources[0x48]	3492	1		T6	2		T8	1		T32	1
valid_sources[0x49]	2603	1		T9	1		T8	1		T31	2
valid_sources[0x4a]	3132	1		T31	2		T32	4		T33	25
valid_sources[0x4b]	3576	1		T6	1		T8	1		T11	1
valid_sources[0x4c]	3215	1		T31	1		T32	4		T33	40
valid_sources[0x4d]	2598	1		T11	1		T31	2		T32	8
valid_sources[0x4e]	2923	1		T11	1		T31	2		T32	2
valid_sources[0x4f]	3531	1		T31	2		T33	21		T34	2
valid_sources[0x50]	2754	1		T9	1		T10	3		T31	3
valid_sources[0x51]	3098	1		T8	1		T31	3		T32	2
valid_sources[0x52]	3272	1		T8	1		T31	2		T32	1
valid_sources[0x53]	2634	1		T10	1		T32	1		T33	23
valid_sources[0x54]	3491	1		T4	3		T5	1		T31	1
valid_sources[0x55]	2910	1		T31	3		T32	1		T33	27
valid_sources[0x56]	3339	1		T2	1		T11	1		T32	1
valid_sources[0x57]	3186	1		T31	3		T33	17		T29	4
valid_sources[0x58]	3046	1		T5	1		T6	1		T31	2
valid_sources[0x59]	2385	1		T8	1		T10	1		T11	2
valid_sources[0x5a]	3513	1		T31	1		T33	26		T29	15
valid_sources[0x5b]	2918	1		T8	1		T31	2		T33	10
valid_sources[0x5c]	3398	1		T2	1		T5	1		T9	1
valid_sources[0x5d]	2911	1		T8	1		T31	2		T33	16
valid_sources[0x5e]	2960	1		T31	2		T33	29		T34	3
valid_sources[0x5f]	3332	1		T6	1		T8	1		T31	1
valid_sources[0x60]	2876	1		T8	1		T31	2		T32	1
valid_sources[0x61]	3279	1		T6	1		T8	1		T11	2
valid_sources[0x62]	2673	1		T11	1		T31	2		T33	19
valid_sources[0x63]	2812	1		T31	2		T32	2		T33	29
valid_sources[0x64]	3311	1		T31	3		T33	19		T34	1
valid_sources[0x65]	2885	1		T31	1		T33	31		T34	3
valid_sources[0x66]	3369	1		T8	1		T31	4		T32	1
valid_sources[0x67]	2796	1		T8	1		T11	2		T31	3
valid_sources[0x68]	3390	1		T6	1		T11	2		T31	3
valid_sources[0x69]	3333	1		T5	1		T6	2		T9	1
valid_sources[0x6a]	2997	1		T5	2		T9	2		T31	1
valid_sources[0x6b]	2625	1		T6	3		T11	1		T31	3
valid_sources[0x6c]	3124	1		T8	1		T11	2		T31	2
valid_sources[0x6d]	3712	1		T6	1		T9	1		T8	1
valid_sources[0x6e]	2697	1		T9	1		T8	1		T31	3
valid_sources[0x6f]	2976	1		T5	1		T8	1		T10	1
valid_sources[0x70]	3028	1		T33	34		T29	4		T30	20
valid_sources[0x71]	3229	1		T4	2		T8	2		T31	1
valid_sources[0x72]	3194	1		T6	1		T31	3		T32	4
valid_sources[0x73]	3199	1		T31	1		T32	1		T33	8
valid_sources[0x74]	2961	1		T33	31		T29	5		T86	5
valid_sources[0x75]	3536	1		T6	1		T31	1		T32	5
valid_sources[0x76]	3301	1		T4	18		T9	2		T11	1
valid_sources[0x77]	2908	1		T31	2		T32	2		T33	31
valid_sources[0x78]	2861	1		T5	1		T31	1		T33	21
valid_sources[0x79]	2999	1		T10	3		T31	2		T32	1
valid_sources[0x7a]	3413	1		T6	2		T32	3		T33	11
valid_sources[0x7b]	2655	1		T9	1		T8	1		T31	2
valid_sources[0x7c]	4028	1		T8	1		T31	3		T32	3
valid_sources[0x7d]	4232	1		T31	2		T32	1		T33	25
valid_sources[0x7e]	3974	1		T9	1		T8	1		T10	1
valid_sources[0x7f]	4240	1		T8	1		T31	1		T32	3
valid_sources[0x80]	2765	1		T4	2		T6	2		T31	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

316360

1

T2

2

T4

9

T6

8

values[0x0]

all_enables

biggest_size

137148

1

T4

20

T5

5

T6

8

values[0x1]

all_enables

biggest_size

136585

1

T4

13

T5

1

T6

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5142	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21680	1		T1	3		T3	1		T12	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10784	1		T31	50		T32	139		T33	27
values[0x0]	7850	1		T1	6		T3	2		T12	5
values[0x1]	8188	1		T1	1		T3	2		T12	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3881	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22941	1		T1	3		T3	2		T12	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	104	1		T32	3		T28	1		T88	1
valid_sources[0x01]	94	1		T132	1		T123	1		T32	3
valid_sources[0x02]	101	1		T133	1		T32	1		T88	4
valid_sources[0x03]	96	1		T134	1		T32	4		T29	3
valid_sources[0x04]	75	1		T133	1		T32	1		T88	3
valid_sources[0x05]	97	1		T135	1		T32	7		T88	3
valid_sources[0x06]	147	1		T136	3		T53	1		T31	28
valid_sources[0x07]	90	1		T123	1		T137	4		T32	2
valid_sources[0x08]	77	1		T32	3		T89	9		T82	2
valid_sources[0x09]	86	1		T32	5		T33	1		T28	3
valid_sources[0x0a]	86	1		T134	1		T32	2		T88	1
valid_sources[0x0b]	97	1		T32	1		T28	2		T82	2
valid_sources[0x0c]	122	1		T138	1		T32	4		T28	2
valid_sources[0x0d]	129	1		T134	3		T139	1		T32	4
valid_sources[0x0e]	101	1		T32	6		T82	2		T23	1
valid_sources[0x0f]	95	1		T79	1		T28	1		T88	4
valid_sources[0x10]	110	1		T32	3		T88	4		T83	2
valid_sources[0x11]	98	1		T123	2		T53	1		T32	3
valid_sources[0x12]	97	1		T35	1		T140	4		T141	1
valid_sources[0x13]	105	1		T138	3		T31	12		T32	1
valid_sources[0x14]	72	1		T57	2		T83	2		T24	4
valid_sources[0x15]	117	1		T88	9		T82	2		T24	2
valid_sources[0x16]	102	1		T32	1		T82	1		T83	1
valid_sources[0x17]	150	1		T142	1		T32	1		T82	1
valid_sources[0x18]	104	1		T57	1		T49	2		T141	1
valid_sources[0x19]	77	1		T32	1		T33	1		T28	2
valid_sources[0x1a]	123	1		T32	2		T82	2		T23	1
valid_sources[0x1b]	57	1		T83	1		T94	3		T143	2
valid_sources[0x1c]	79	1		T53	1		T32	3		T33	2
valid_sources[0x1d]	103	1		T17	1		T135	1		T88	3
valid_sources[0x1e]	61	1		T32	1		T83	1		T94	2
valid_sources[0x1f]	111	1		T136	1		T32	5		T28	1
valid_sources[0x20]	93	1		T58	5		T32	1		T88	3
valid_sources[0x21]	80	1		T138	1		T28	1		T82	2
valid_sources[0x22]	154	1		T144	3		T32	2		T30	2
valid_sources[0x23]	64	1		T32	3		T82	2		T24	2
valid_sources[0x24]	66	1		T32	1		T28	2		T82	4
valid_sources[0x25]	95	1		T32	3		T82	1		T23	1
valid_sources[0x26]	85	1		T32	2		T28	2		T82	2
valid_sources[0x27]	86	1		T27	4		T32	4		T33	1
valid_sources[0x28]	107	1		T138	1		T31	4		T32	1
valid_sources[0x29]	83	1		T133	1		T88	4		T81	1
valid_sources[0x2a]	106	1		T33	1		T28	3		T88	6
valid_sources[0x2b]	85	1		T133	1		T140	1		T33	1
valid_sources[0x2c]	84	1		T45	6		T32	4		T88	2
valid_sources[0x2d]	87	1		T145	9		T32	1		T82	1
valid_sources[0x2e]	112	1		T79	2		T32	2		T82	1
valid_sources[0x2f]	89	1		T134	1		T136	2		T32	4
valid_sources[0x30]	306	1		T31	4		T32	3		T28	1
valid_sources[0x31]	136	1		T32	1		T88	4		T82	1
valid_sources[0x32]	96	1		T14	9		T32	4		T87	1
valid_sources[0x33]	91	1		T28	1		T29	5		T88	4
valid_sources[0x34]	107	1		T140	1		T146	1		T32	1
valid_sources[0x35]	96	1		T72	4		T32	5		T33	1
valid_sources[0x36]	87	1		T137	2		T31	1		T28	2
valid_sources[0x37]	87	1		T49	4		T32	2		T88	2
valid_sources[0x38]	77	1		T31	7		T32	5		T28	1
valid_sources[0x39]	86	1		T147	6		T53	1		T32	3
valid_sources[0x3a]	154	1		T82	1		T23	1		T24	1
valid_sources[0x3b]	203	1		T32	4		T23	1		T24	6
valid_sources[0x3c]	124	1		T12	4		T136	1		T138	1
valid_sources[0x3d]	95	1		T142	1		T32	3		T88	2
valid_sources[0x3e]	99	1		T12	2		T32	3		T33	1
valid_sources[0x3f]	92	1		T28	3		T88	2		T82	1
valid_sources[0x40]	96	1		T32	2		T28	5		T83	1
valid_sources[0x41]	54	1		T132	1		T29	2		T82	2
valid_sources[0x42]	116	1		T123	1		T135	2		T32	1
valid_sources[0x43]	86	1		T139	1		T32	2		T24	9
valid_sources[0x44]	103	1		T32	2		T28	6		T82	2
valid_sources[0x45]	105	1		T30	1		T88	1		T23	1
valid_sources[0x46]	102	1		T133	1		T32	1		T33	1
valid_sources[0x47]	166	1		T138	2		T31	4		T32	6
valid_sources[0x48]	120	1		T3	4		T144	2		T28	1
valid_sources[0x49]	153	1		T135	2		T32	3		T28	2
valid_sources[0x4a]	70	1		T49	1		T32	1		T28	1
valid_sources[0x4b]	83	1		T139	1		T32	3		T82	3
valid_sources[0x4c]	110	1		T32	2		T28	2		T83	2
valid_sources[0x4d]	72	1		T32	1		T28	2		T83	1
valid_sources[0x4e]	150	1		T32	5		T89	3		T81	1
valid_sources[0x4f]	88	1		T35	1		T32	4		T24	11
valid_sources[0x50]	58	1		T16	6		T139	1		T82	1
valid_sources[0x51]	77	1		T28	1		T82	1		T94	1
valid_sources[0x52]	104	1		T52	9		T32	2		T83	1
valid_sources[0x53]	129	1		T57	2		T31	24		T32	2
valid_sources[0x54]	85	1		T140	3		T32	1		T33	1
valid_sources[0x55]	91	1		T32	1		T82	1		T85	5
valid_sources[0x56]	112	1		T32	3		T33	1		T28	3
valid_sources[0x57]	111	1		T33	1		T29	2		T82	2
valid_sources[0x58]	118	1		T48	13		T136	1		T32	5
valid_sources[0x59]	106	1		T18	1		T60	10		T32	6
valid_sources[0x5a]	85	1		T32	1		T30	3		T82	1
valid_sources[0x5b]	87	1		T33	1		T82	2		T83	2
valid_sources[0x5c]	112	1		T32	3		T29	3		T82	1
valid_sources[0x5d]	102	1		T32	2		T82	1		T83	1
valid_sources[0x5e]	108	1		T32	2		T28	1		T88	3
valid_sources[0x5f]	103	1		T32	3		T23	1		T24	15
valid_sources[0x60]	71	1		T32	1		T82	1		T84	5
valid_sources[0x61]	127	1		T32	2		T28	1		T88	1
valid_sources[0x62]	74	1		T32	2		T28	1		T29	1
valid_sources[0x63]	73	1		T141	3		T32	2		T82	1
valid_sources[0x64]	106	1		T32	2		T28	1		T82	2
valid_sources[0x65]	303	1		T31	1		T32	1		T30	238
valid_sources[0x66]	98	1		T32	1		T88	1		T83	1
valid_sources[0x67]	109	1		T53	1		T32	4		T88	7
valid_sources[0x68]	89	1		T32	1		T33	1		T28	2
valid_sources[0x69]	78	1		T132	1		T32	3		T33	2
valid_sources[0x6a]	123	1		T31	15		T32	3		T33	1
valid_sources[0x6b]	105	1		T32	1		T33	2		T88	3
valid_sources[0x6c]	112	1		T32	2		T82	4		T83	2
valid_sources[0x6d]	89	1		T142	1		T32	4		T28	1
valid_sources[0x6e]	88	1		T17	3		T33	1		T88	3
valid_sources[0x6f]	111	1		T132	1		T32	1		T28	1
valid_sources[0x70]	83	1		T148	9		T32	3		T89	6
valid_sources[0x71]	104	1		T138	1		T32	5		T24	20
valid_sources[0x72]	76	1		T144	2		T32	2		T33	4
valid_sources[0x73]	187	1		T137	1		T32	7		T28	1
valid_sources[0x74]	94	1		T32	1		T88	12		T82	1
valid_sources[0x75]	93	1		T53	1		T32	2		T28	1
valid_sources[0x76]	89	1		T137	2		T32	1		T33	2
valid_sources[0x77]	90	1		T134	1		T32	1		T28	1
valid_sources[0x78]	86	1		T149	2		T32	6		T82	4
valid_sources[0x79]	104	1		T31	14		T32	1		T88	1
valid_sources[0x7a]	135	1		T134	4		T31	2		T32	2
valid_sources[0x7b]	123	1		T32	2		T82	1		T84	5
valid_sources[0x7c]	90	1		T18	1		T31	1		T32	2
valid_sources[0x7d]	84	1		T32	1		T82	1		T83	1
valid_sources[0x7e]	77	1		T32	1		T82	3		T24	4
valid_sources[0x7f]	116	1		T142	1		T32	3		T28	1
valid_sources[0x80]	86	1		T132	1		T32	2		T83	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7537

1

T31

42

T32

136

T33

27

values[0x0]

all_enables

biggest_size

7144

1

T1

3

T12

5

T16

2

values[0x1]

all_enables

biggest_size

6999

1

T3

1

T14

1

T15

1