Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
269933 |
1 |
|
T2 |
7 |
|
T4 |
41 |
|
T5 |
33 |
full_word |
591880 |
1 |
|
T2 |
2 |
|
T4 |
42 |
|
T5 |
6 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
861523 |
1 |
|
T2 |
9 |
|
T4 |
83 |
|
T5 |
39 |
auto[TlIntgErrCmd] |
82 |
1 |
|
T29 |
2 |
|
T119 |
4 |
|
T122 |
2 |
auto[TlIntgErrData] |
110 |
1 |
|
T29 |
3 |
|
T119 |
12 |
|
T122 |
4 |
auto[TlIntgErrBoth] |
98 |
1 |
|
T29 |
5 |
|
T119 |
4 |
|
T122 |
4 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
540405 |
1 |
|
T2 |
8 |
|
T4 |
20 |
|
T6 |
18 |
auto[1] |
321408 |
1 |
|
T2 |
1 |
|
T4 |
63 |
|
T5 |
39 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
223734 |
1 |
|
T2 |
6 |
|
T4 |
11 |
|
T6 |
10 |
auto[TlIntgErrNone] |
partial |
auto[1] |
45938 |
1 |
|
T2 |
1 |
|
T4 |
30 |
|
T5 |
33 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
316551 |
1 |
|
T2 |
2 |
|
T4 |
9 |
|
T6 |
8 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
275300 |
1 |
|
T4 |
33 |
|
T5 |
6 |
|
T6 |
11 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
32 |
1 |
|
T29 |
2 |
|
T125 |
2 |
|
T61 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
42 |
1 |
|
T119 |
4 |
|
T122 |
2 |
|
T125 |
4 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
4 |
1 |
|
T61 |
1 |
|
T130 |
1 |
|
T127 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
T125 |
1 |
|
T61 |
1 |
|
T130 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
41 |
1 |
|
T29 |
2 |
|
T119 |
6 |
|
T125 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
58 |
1 |
|
T29 |
1 |
|
T119 |
4 |
|
T122 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
5 |
1 |
|
T119 |
1 |
|
T61 |
1 |
|
T129 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
6 |
1 |
|
T119 |
1 |
|
T122 |
1 |
|
T61 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
30 |
1 |
|
T29 |
3 |
|
T119 |
1 |
|
T122 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
58 |
1 |
|
T29 |
2 |
|
T119 |
3 |
|
T122 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
8 |
1 |
|
T61 |
1 |
|
T131 |
1 |
|
T128 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
2 |
1 |
|
T129 |
1 |
|
T66 |
1 |
|
- |
- |