Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.64	100.00	55.32	85.38		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	33111876	14996	0	0
late_debug_enable_rd_A	33111876	3339	0	0
late_debug_enable_regwen_rd_A	33111876	3955	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33111876	14996	0	0
T28	6855	32	0	0
T29	15774	3	0	0
T30	134012	285	0	0
T31	7444	484	0	0
T32	15104	454	0	0
T81	7924	172	0	0
T82	5690	85	0	0
T83	7359	590	0	0
T84	219019	6	0	0
T85	41404	75	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33111876	3339	0	0
T28	6855	44	0	0
T32	15104	144	0	0
T34	4726	1	0	0
T84	219019	1	0	0
T90	4809	2	0	0
T96	9812	2	0	0
T110	47232	40	0	0
T117	20048	185	0	0
T118	6783	17	0	0
T119	113159	100	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33111876	3955	0	0
T28	6855	39	0	0
T32	15104	149	0	0
T34	4726	1	0	0
T90	4809	7	0	0
T97	14725	8	0	0
T110	47232	61	0	0
T117	20048	159	0	0
T118	6783	6	0	0
T119	113159	64	0	0
T120	7828	11	0	0