Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
1 | 1 | Covered | T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
11206820 |
11206142 |
0 |
0 |
selKnown1 |
12182648 |
12181970 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11206820 |
11206142 |
0 |
0 |
T1 |
314 |
312 |
0 |
0 |
T2 |
3208 |
3206 |
0 |
0 |
T3 |
310 |
308 |
0 |
0 |
T4 |
144118 |
144114 |
0 |
0 |
T5 |
0 |
11 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
2 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
25 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T12 |
352 |
350 |
0 |
0 |
T14 |
374 |
372 |
0 |
0 |
T15 |
378 |
376 |
0 |
0 |
T16 |
338 |
334 |
0 |
0 |
T17 |
358 |
354 |
0 |
0 |
T18 |
312 |
308 |
0 |
0 |
T19 |
0 |
20 |
0 |
0 |
T20 |
0 |
40 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T27 |
2 |
0 |
0 |
0 |
T48 |
2 |
0 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T79 |
2 |
0 |
0 |
0 |
T80 |
2 |
0 |
0 |
0 |
T121 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12182648 |
12181970 |
0 |
0 |
T1 |
1573 |
1571 |
0 |
0 |
T2 |
5675 |
5673 |
0 |
0 |
T3 |
1918 |
1916 |
0 |
0 |
T4 |
261287 |
261283 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
2 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T12 |
2248 |
2246 |
0 |
0 |
T14 |
1813 |
1811 |
0 |
0 |
T15 |
3344 |
3342 |
0 |
0 |
T16 |
2131 |
2127 |
0 |
0 |
T17 |
1780 |
1776 |
0 |
0 |
T18 |
1413 |
1409 |
0 |
0 |
T19 |
0 |
20 |
0 |
0 |
T20 |
0 |
40 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T27 |
2 |
0 |
0 |
0 |
T48 |
2 |
0 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T79 |
2 |
0 |
0 |
0 |
T80 |
2 |
0 |
0 |
0 |
T121 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
1 | 1 | Covered | T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
377166 |
377101 |
0 |
0 |
selKnown1 |
1353141 |
1353076 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
377166 |
377101 |
0 |
0 |
T1 |
157 |
156 |
0 |
0 |
T2 |
1604 |
1603 |
0 |
0 |
T3 |
155 |
154 |
0 |
0 |
T4 |
71904 |
71903 |
0 |
0 |
T12 |
176 |
175 |
0 |
0 |
T14 |
187 |
186 |
0 |
0 |
T15 |
189 |
188 |
0 |
0 |
T16 |
168 |
167 |
0 |
0 |
T17 |
178 |
177 |
0 |
0 |
T18 |
155 |
154 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1353141 |
1353076 |
0 |
0 |
T1 |
1416 |
1415 |
0 |
0 |
T2 |
4071 |
4070 |
0 |
0 |
T3 |
1763 |
1762 |
0 |
0 |
T4 |
189089 |
189088 |
0 |
0 |
T12 |
2072 |
2071 |
0 |
0 |
T14 |
1626 |
1625 |
0 |
0 |
T15 |
3155 |
3154 |
0 |
0 |
T16 |
1961 |
1960 |
0 |
0 |
T17 |
1600 |
1599 |
0 |
0 |
T18 |
1256 |
1255 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
1 | 1 | Covered | T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
154 |
89 |
0 |
0 |
T4 |
9 |
8 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T20 |
0 |
20 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T80 |
1 |
0 |
0 |
0 |
T121 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
147 |
82 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T20 |
0 |
20 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T80 |
1 |
0 |
0 |
0 |
T121 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
1 | 1 | Covered | T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10827931 |
10827657 |
0 |
0 |
selKnown1 |
10827931 |
10827657 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10827931 |
10827657 |
0 |
0 |
T1 |
157 |
156 |
0 |
0 |
T2 |
1604 |
1603 |
0 |
0 |
T3 |
155 |
154 |
0 |
0 |
T4 |
72194 |
72193 |
0 |
0 |
T12 |
176 |
175 |
0 |
0 |
T14 |
187 |
186 |
0 |
0 |
T15 |
189 |
188 |
0 |
0 |
T16 |
168 |
167 |
0 |
0 |
T17 |
178 |
177 |
0 |
0 |
T18 |
155 |
154 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10827931 |
10827657 |
0 |
0 |
T1 |
157 |
156 |
0 |
0 |
T2 |
1604 |
1603 |
0 |
0 |
T3 |
155 |
154 |
0 |
0 |
T4 |
72194 |
72193 |
0 |
0 |
T12 |
176 |
175 |
0 |
0 |
T14 |
187 |
186 |
0 |
0 |
T15 |
189 |
188 |
0 |
0 |
T16 |
168 |
167 |
0 |
0 |
T17 |
178 |
177 |
0 |
0 |
T18 |
155 |
154 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4 |
1 | 1 | Covered | T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1569 |
1295 |
0 |
0 |
selKnown1 |
1429 |
1155 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1569 |
1295 |
0 |
0 |
T4 |
11 |
10 |
0 |
0 |
T5 |
0 |
10 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
21 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T20 |
0 |
20 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T80 |
1 |
0 |
0 |
0 |
T121 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1429 |
1155 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T16 |
1 |
0 |
0 |
0 |
T17 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
0 |
10 |
0 |
0 |
T20 |
0 |
20 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T48 |
1 |
0 |
0 |
0 |
T55 |
0 |
10 |
0 |
0 |
T79 |
1 |
0 |
0 |
0 |
T80 |
1 |
0 |
0 |
0 |
T121 |
1 |
0 |
0 |
0 |