Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack	77.24	100.00	66.67			92.31	50.00
tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack	79.17	100.00	66.67			100.00	50.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.24	100.00	66.67			92.31	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.98	100.00	66.67			95.24	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.78	100.00	93.33			100.00		i_cdc_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_rz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	87.50			100.00		i_cdc_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_rz_hs_protocol.req_sync	100.00	100.00				100.00

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	55	0	0
ALWAYS	75	10	10	100.00
ALWAYS	117	3	3	100.00
ALWAYS	126	11	11	100.00
ALWAYS	169	3	3	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
77	1	1
79	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
126	1	1
127	1	1
128	1	1
130	1	1
132	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
			MISSING_ELSE
143	1	1
145	1	1
146	1	1
			MISSING_ELSE
169	1	1
170	1	1
172	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
CASE	79	4	4	100.00
IF	117	2	2	100.00
CASE	130	5	5	100.00
IF	169	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	case (gen_rz_hs_protocol.src_fsm_q)
-2-:	83	if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-:	93	if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:

-1-	-2-	-3-	Status	Tests
LoSt	1	-	Covered	T1,T2,T3
LoSt	0	-	Covered	T1,T2,T3
HiSt	-	1	Covered	T1,T2,T3
HiSt	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	case (gen_rz_hs_protocol.dst_fsm_q)
-2-:	132	if (gen_rz_hs_protocol.dst_req)
-3-:	137	if (dst_ack_i)
-4-:	145	if ((!gen_rz_hs_protocol.dst_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
LoSt	1	1	-	Covered	T1,T2,T3
LoSt	1	0	-	Covered	T1,T2,T3
LoSt	0	-	-	Covered	T1,T2,T3
HiSt	-	-	1	Covered	T1,T2,T3
HiSt	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	43939807	92590	0	0
SyncReqAckHoldReq	43939807	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	43939807	92590	0	0
T1	1573	2	0	0
T2	5675	20	0	0
T3	1918	2	0	0
T4	261283	612	0	0
T12	2248	2	0	0
T14	1813	2	0	0
T15	3344	2	0	0
T16	2129	2	0	0
T17	1778	2	0	0
T18	1411	2	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	43939807	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	55	0	0
ALWAYS	75	10	10	100.00
ALWAYS	117	3	3	100.00
ALWAYS	126	11	11	100.00
ALWAYS	169	3	3	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
77	1	1
79	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
126	1	1
127	1	1
128	1	1
130	1	1
132	1	1
134	1	1
137	1	1
138	1	1
			==> MISSING_ELSE
			MISSING_ELSE
143	1	1
145	1	1
146	1	1
			MISSING_ELSE
169	1	1
170	1	1
172	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		13	12	92.31
CASE	79	4	4	100.00
IF	117	2	2	100.00
CASE	130	5	4	80.00
IF	169	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	case (gen_rz_hs_protocol.src_fsm_q)
-2-:	83	if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-:	93	if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:

-1-	-2-	-3-	Status	Tests
LoSt	1	-	Covered	T1,T2,T3
LoSt	0	-	Covered	T1,T2,T3
HiSt	-	1	Covered	T1,T2,T3
HiSt	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	case (gen_rz_hs_protocol.dst_fsm_q)
-2-:	132	if (gen_rz_hs_protocol.dst_req)
-3-:	137	if (dst_ack_i)
-4-:	145	if ((!gen_rz_hs_protocol.dst_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
LoSt	1	1	-	Covered	T1,T2,T3
LoSt	1	0	-	Not Covered
LoSt	0	-	-	Covered	T1,T2,T3
HiSt	-	-	1	Covered	T1,T2,T3
HiSt	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	10827931	46295	0	0
SyncReqAckHoldReq	33111876	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827931	46295	0	0
T1	157	1	0	0
T2	1604	10	0	0
T3	155	1	0	0
T4	72194	306	0	0
T12	176	1	0	0
T14	187	1	0	0
T15	189	1	0	0
T16	168	1	0	0
T17	178	1	0	0
T18	155	1	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	33111876	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	55	0	0
ALWAYS	75	10	10	100.00
ALWAYS	117	3	3	100.00
ALWAYS	126	11	11	100.00
ALWAYS	169	3	3	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
77	1	1
79	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
126	1	1
127	1	1
128	1	1
130	1	1
132	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
			MISSING_ELSE
143	1	1
145	1	1
146	1	1
			MISSING_ELSE
169	1	1
170	1	1
172	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
CASE	79	4	4	100.00
IF	117	2	2	100.00
CASE	130	5	5	100.00
IF	169	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	case (gen_rz_hs_protocol.src_fsm_q)
-2-:	83	if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-:	93	if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:

-1-	-2-	-3-	Status	Tests
LoSt	1	-	Covered	T1,T2,T3
LoSt	0	-	Covered	T1,T2,T3
HiSt	-	1	Covered	T1,T2,T3
HiSt	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	case (gen_rz_hs_protocol.dst_fsm_q)
-2-:	132	if (gen_rz_hs_protocol.dst_req)
-3-:	137	if (dst_ack_i)
-4-:	145	if ((!gen_rz_hs_protocol.dst_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
LoSt	1	1	-	Covered	T1,T2,T3
LoSt	1	0	-	Covered	T1,T2,T3
LoSt	0	-	-	Covered	T1,T2,T3
HiSt	-	-	1	Covered	T1,T2,T3
HiSt	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	33111876	46295	0	0
SyncReqAckHoldReq	10827931	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	33111876	46295	0	0
T1	1416	1	0	0
T2	4071	10	0	0
T3	1763	1	0	0
T4	189089	306	0	0
T12	2072	1	0	0
T14	1626	1	0	0
T15	3155	1	0	0
T16	1961	1	0	0
T17	1600	1	0	0
T18	1256	1	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	10827931	0	0	0