SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
74.27 | 90.58 | 76.10 | 86.17 | 58.97 | 77.00 | 98.42 | 32.67 |
T252 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.936526542 | May 23 03:35:39 PM PDT 24 | May 23 03:35:47 PM PDT 24 | 162555493 ps | ||
T253 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3430648833 | May 23 03:35:12 PM PDT 24 | May 23 03:35:19 PM PDT 24 | 139711527 ps | ||
T68 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1139706547 | May 23 03:35:40 PM PDT 24 | May 23 03:35:42 PM PDT 24 | 40086798 ps | ||
T254 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.789732064 | May 23 03:35:29 PM PDT 24 | May 23 03:35:35 PM PDT 24 | 481586945 ps | ||
T255 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2917389512 | May 23 03:35:43 PM PDT 24 | May 23 03:35:51 PM PDT 24 | 970278528 ps | ||
T256 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.146055772 | May 23 03:35:44 PM PDT 24 | May 23 03:36:01 PM PDT 24 | 23179986955 ps | ||
T257 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2252266552 | May 23 03:35:40 PM PDT 24 | May 23 03:35:51 PM PDT 24 | 944227376 ps | ||
T258 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2792950165 | May 23 03:35:35 PM PDT 24 | May 23 03:35:38 PM PDT 24 | 89097364 ps | ||
T259 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.114469233 | May 23 03:35:12 PM PDT 24 | May 23 03:35:19 PM PDT 24 | 58531071 ps | ||
T260 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3418608423 | May 23 03:35:48 PM PDT 24 | May 23 03:35:55 PM PDT 24 | 838903849 ps | ||
T261 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.180888793 | May 23 03:35:28 PM PDT 24 | May 23 03:37:18 PM PDT 24 | 54359552938 ps | ||
T262 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1786471770 | May 23 03:35:43 PM PDT 24 | May 23 03:35:56 PM PDT 24 | 880434584 ps | ||
T263 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2088546071 | May 23 03:35:25 PM PDT 24 | May 23 03:36:10 PM PDT 24 | 10850224530 ps | ||
T264 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2648219286 | May 23 03:35:26 PM PDT 24 | May 23 03:35:32 PM PDT 24 | 406017402 ps | ||
T265 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3054735202 | May 23 03:35:06 PM PDT 24 | May 23 03:35:11 PM PDT 24 | 130546100 ps | ||
T266 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.767278166 | May 23 03:35:11 PM PDT 24 | May 23 03:35:25 PM PDT 24 | 410116582 ps | ||
T267 | /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2978141022 | May 23 03:36:00 PM PDT 24 | May 23 03:37:11 PM PDT 24 | 20373051728 ps | ||
T268 | /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2634863680 | May 23 03:35:55 PM PDT 24 | May 23 03:36:27 PM PDT 24 | 7954448968 ps | ||
T269 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2927874063 | May 23 03:35:48 PM PDT 24 | May 23 03:36:12 PM PDT 24 | 1322148824 ps | ||
T270 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3866503990 | May 23 03:35:48 PM PDT 24 | May 23 03:35:56 PM PDT 24 | 208840194 ps | ||
T271 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.87963102 | May 23 03:35:41 PM PDT 24 | May 23 03:35:46 PM PDT 24 | 827407366 ps | ||
T272 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.329118951 | May 23 03:35:27 PM PDT 24 | May 23 03:35:39 PM PDT 24 | 978545781 ps | ||
T273 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2093541113 | May 23 03:35:13 PM PDT 24 | May 23 03:35:19 PM PDT 24 | 30959869 ps | ||
T274 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.758080944 | May 23 03:35:24 PM PDT 24 | May 23 03:36:05 PM PDT 24 | 24443711968 ps | ||
T275 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.844190386 | May 23 03:35:43 PM PDT 24 | May 23 03:35:48 PM PDT 24 | 54448335 ps | ||
T276 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2649341028 | May 23 03:35:25 PM PDT 24 | May 23 03:35:28 PM PDT 24 | 144824198 ps | ||
T277 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3406454261 | May 23 03:35:29 PM PDT 24 | May 23 03:35:33 PM PDT 24 | 39213413 ps | ||
T278 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1943896164 | May 23 03:35:50 PM PDT 24 | May 23 03:36:00 PM PDT 24 | 4152035266 ps | ||
T279 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2341327974 | May 23 03:35:43 PM PDT 24 | May 23 03:35:51 PM PDT 24 | 2889555960 ps | ||
T280 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3476041727 | May 23 03:35:26 PM PDT 24 | May 23 03:35:55 PM PDT 24 | 16324062176 ps | ||
T281 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3578672531 | May 23 03:35:14 PM PDT 24 | May 23 03:35:23 PM PDT 24 | 906530823 ps |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.2849283705 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 3257249167 ps |
CPU time | 6.97 seconds |
Started | May 23 03:31:44 PM PDT 24 |
Finished | May 23 03:31:55 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-36494324-3dc1-42d0-b2d6-3516a4d591ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849283705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2849283705 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.828500794 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 875279040 ps |
CPU time | 1.29 seconds |
Started | May 23 03:30:47 PM PDT 24 |
Finished | May 23 03:30:51 PM PDT 24 |
Peak memory | 229100 kb |
Host | smart-11cda344-5859-4218-a63e-dc28bf4a9c6a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828500794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.828500794 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2382238438 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 15929682179 ps |
CPU time | 47.73 seconds |
Started | May 23 03:35:56 PM PDT 24 |
Finished | May 23 03:36:49 PM PDT 24 |
Peak memory | 221640 kb |
Host | smart-9711edd6-7672-479c-acf7-786ddcfe9751 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382238438 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.2382238438 |
Directory | /workspace/18.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.2887565235 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 3094380182 ps |
CPU time | 6.16 seconds |
Started | May 23 03:31:48 PM PDT 24 |
Finished | May 23 03:31:58 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-92ef8bb8-9526-4563-a64d-0adab27d9deb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887565235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2887565235 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.4209472581 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 59038860 ps |
CPU time | 0.7 seconds |
Started | May 23 03:31:23 PM PDT 24 |
Finished | May 23 03:31:27 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-4da39117-b3bb-42f4-897a-0fda2ec5add6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209472581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.4209472581 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4287087625 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 519459597 ps |
CPU time | 15.99 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:58 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-69d2ed14-34cd-4abe-a899-e46bdd450a74 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287087625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4287087625 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2982630904 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 712003332 ps |
CPU time | 2.04 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:30 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-8482130d-abbd-465f-a1f4-2380a4291c47 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982630904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2982630904 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2276899217 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 8014857650 ps |
CPU time | 13.56 seconds |
Started | May 23 03:31:48 PM PDT 24 |
Finished | May 23 03:32:05 PM PDT 24 |
Peak memory | 213152 kb |
Host | smart-63bf9b46-4a5b-4b9b-aff1-097b329b4ca5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276899217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2276899217 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.712580732 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 12800715603 ps |
CPU time | 13.51 seconds |
Started | May 23 03:35:09 PM PDT 24 |
Finished | May 23 03:35:27 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-538fe31f-e0c1-4747-9f13-759ac5d7316f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712580732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.712580732 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1965606960 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1804930244 ps |
CPU time | 18.89 seconds |
Started | May 23 03:35:49 PM PDT 24 |
Finished | May 23 03:36:13 PM PDT 24 |
Peak memory | 221436 kb |
Host | smart-3dada680-468c-4581-929e-408668d1b818 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965606960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 965606960 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3946815282 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 54640317 ps |
CPU time | 2.2 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 221476 kb |
Host | smart-fa887354-ad27-41a1-9309-a8555c6cd6fd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946815282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3946815282 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2831757818 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 8924119718 ps |
CPU time | 16.14 seconds |
Started | May 23 03:35:56 PM PDT 24 |
Finished | May 23 03:36:18 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-845bb73c-ae33-4659-98bf-bcbaf096d419 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831757818 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.2831757818 |
Directory | /workspace/22.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.2936907982 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 51308836 ps |
CPU time | 0.89 seconds |
Started | May 23 03:30:48 PM PDT 24 |
Finished | May 23 03:30:52 PM PDT 24 |
Peak memory | 212596 kb |
Host | smart-bd00c696-3e1f-48cf-a727-8b26a9333d25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936907982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2936907982 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.100635400 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1351877538 ps |
CPU time | 3.29 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-13241ba5-fd07-47f5-868c-8bcfe9e678be |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100635400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _hw_reset.100635400 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.2816385799 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 11908131338 ps |
CPU time | 18.32 seconds |
Started | May 23 03:31:46 PM PDT 24 |
Finished | May 23 03:32:09 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-eab5bb03-7868-44e6-a5b5-20b4fe5bf924 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816385799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2816385799 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1422114798 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 619002884 ps |
CPU time | 8.09 seconds |
Started | May 23 03:35:54 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-4cabdd90-d942-4bc8-bd0f-728bafcd4a18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422114798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.1422114798 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1756225101 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1916514393 ps |
CPU time | 17.37 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:36:05 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-7c66398f-7b6b-4c46-8d3f-5818223f4601 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756225101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1 756225101 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1051351362 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 10827853263 ps |
CPU time | 35.85 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 220160 kb |
Host | smart-1caf7cf9-57fe-4eef-875a-bbadc0ae7f15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051351362 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1051351362 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1174382436 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 122296777 ps |
CPU time | 0.89 seconds |
Started | May 23 03:30:33 PM PDT 24 |
Finished | May 23 03:30:36 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-cff9a5e4-e972-4946-a6b9-9a967a4f32e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174382436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1174382436 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3190429137 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 742560418 ps |
CPU time | 8.94 seconds |
Started | May 23 03:35:47 PM PDT 24 |
Finished | May 23 03:36:01 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-7fda3758-bbce-418f-87a8-04ec67fcddec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190429137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3 190429137 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3754677858 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 23794380 ps |
CPU time | 0.74 seconds |
Started | May 23 03:31:44 PM PDT 24 |
Finished | May 23 03:31:49 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-5c975717-8abb-4916-8bbd-1c177c9cd4bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754677858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3754677858 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1341039650 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 7381954365 ps |
CPU time | 25.87 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:36:20 PM PDT 24 |
Peak memory | 221448 kb |
Host | smart-90af2ef2-4e1f-4720-aae8-de7a7412d5e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341039650 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.1341039650 |
Directory | /workspace/16.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.951787863 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 20793120153 ps |
CPU time | 22.22 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 227668 kb |
Host | smart-31352734-9c71-4d87-9458-467182e897af |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951787863 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.951787863 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1435817892 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 3072347357 ps |
CPU time | 18.08 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 221496 kb |
Host | smart-2776ac9a-fff5-47e9-8df8-0f5a824cd1ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435817892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1435817892 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.3521961484 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 9755008119 ps |
CPU time | 19.79 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 214684 kb |
Host | smart-351faf24-3993-40f9-9893-425a2c3ae6ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521961484 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.3521961484 |
Directory | /workspace/17.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1849162829 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 2662169185 ps |
CPU time | 3.66 seconds |
Started | May 23 03:35:07 PM PDT 24 |
Finished | May 23 03:35:15 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-4419ce50-78fe-4b3d-9bf2-2b3e330c4bda |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849162829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1849162829 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1561996670 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 506839937 ps |
CPU time | 2.94 seconds |
Started | May 23 03:35:08 PM PDT 24 |
Finished | May 23 03:35:15 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-8b73cc07-23b3-4fa6-9423-dadca018e729 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561996670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.1561996670 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3834015916 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 58308898 ps |
CPU time | 2.12 seconds |
Started | May 23 03:35:32 PM PDT 24 |
Finished | May 23 03:35:36 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-1cf506f3-5958-4f47-abe0-0c7f7d20ded7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834015916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3834015916 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1130923652 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1221918491 ps |
CPU time | 10.38 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:35:38 PM PDT 24 |
Peak memory | 221480 kb |
Host | smart-3154def3-0d2a-4d66-a89a-968985a99d66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130923652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1130923652 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3667880273 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 2779529920 ps |
CPU time | 3.23 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 215608 kb |
Host | smart-802f2ca5-5b24-424d-9b48-c945f98f0ebf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667880273 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3667880273 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.1329146296 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 12127484632 ps |
CPU time | 13.78 seconds |
Started | May 23 03:35:54 PM PDT 24 |
Finished | May 23 03:36:12 PM PDT 24 |
Peak memory | 219904 kb |
Host | smart-e91ef1bf-5270-4171-ae50-d0bdc38cbeae |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329146296 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.1329146296 |
Directory | /workspace/30.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.399227646 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 7182194429 ps |
CPU time | 15.44 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:19 PM PDT 24 |
Peak memory | 221564 kb |
Host | smart-27235eae-4c01-49d8-a037-d88cdc1e9e84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399227646 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.399227646 |
Directory | /workspace/33.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2848335168 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 2006682828 ps |
CPU time | 3.26 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:36 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-dd36c1f6-b15e-48e6-bfa6-34ee760fe104 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848335168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2848335168 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1139706547 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 40086798 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:40 PM PDT 24 |
Finished | May 23 03:35:42 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-1a90cfab-a382-4b32-8f9e-ef328a335b86 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139706547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 139706547 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.173610641 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 20192093 ps |
CPU time | 0.78 seconds |
Started | May 23 03:30:37 PM PDT 24 |
Finished | May 23 03:30:40 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-8c9b428f-3ab9-4538-bc6f-d35ce8496b58 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173610641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.173610641 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2137610672 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 4123168721 ps |
CPU time | 26.84 seconds |
Started | May 23 03:35:09 PM PDT 24 |
Finished | May 23 03:35:40 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-88b55bef-bbe1-4fbc-b430-394180838169 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137610672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2137610672 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3523621812 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 115815036 ps |
CPU time | 2.27 seconds |
Started | May 23 03:35:08 PM PDT 24 |
Finished | May 23 03:35:15 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-7e5d730f-d9b8-4c61-b4d1-eb69a36f9f97 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523621812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3523621812 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4246556748 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 1695417082 ps |
CPU time | 5.98 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:36 PM PDT 24 |
Peak memory | 216792 kb |
Host | smart-0a1d98e5-4ba4-4068-88c6-7f4b35209aa8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246556748 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.4246556748 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3430648833 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 139711527 ps |
CPU time | 2.04 seconds |
Started | May 23 03:35:12 PM PDT 24 |
Finished | May 23 03:35:19 PM PDT 24 |
Peak memory | 218192 kb |
Host | smart-753097c0-7a68-4c98-a5ae-8c6a3a45560f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430648833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3430648833 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2250524227 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 10357046924 ps |
CPU time | 45.91 seconds |
Started | May 23 03:35:13 PM PDT 24 |
Finished | May 23 03:36:05 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-8d63d7df-851e-4434-8370-f585bcf5c640 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250524227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.2250524227 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3578672531 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 906530823 ps |
CPU time | 3.82 seconds |
Started | May 23 03:35:14 PM PDT 24 |
Finished | May 23 03:35:23 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-0f6506d6-3586-4e94-88b7-50d830803cc5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578672531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 578672531 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.687637401 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 36099657 ps |
CPU time | 0.75 seconds |
Started | May 23 03:35:10 PM PDT 24 |
Finished | May 23 03:35:17 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-53927e08-0a42-465e-847c-ef1c06d4f164 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687637401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _aliasing.687637401 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.680833894 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 78706178 ps |
CPU time | 0.72 seconds |
Started | May 23 03:35:13 PM PDT 24 |
Finished | May 23 03:35:20 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-02777870-98bc-488e-8afa-175a44b73c35 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680833894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _hw_reset.680833894 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.114469233 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 58531071 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:12 PM PDT 24 |
Finished | May 23 03:35:19 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-4cc1e935-4365-49c4-8fe0-d916e4ca8575 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114469233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.114469233 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1379302586 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 34093855 ps |
CPU time | 0.68 seconds |
Started | May 23 03:35:11 PM PDT 24 |
Finished | May 23 03:35:18 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-716a0cf8-bbc0-414d-b7ac-fe10addf8bf4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379302586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1379302586 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2093541113 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 30959869 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:13 PM PDT 24 |
Finished | May 23 03:35:19 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-98e2ee5e-488d-47d1-800d-24c97fa928f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093541113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2093541113 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3520328320 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 201702898 ps |
CPU time | 3.9 seconds |
Started | May 23 03:35:09 PM PDT 24 |
Finished | May 23 03:35:17 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-82ebc65c-c355-451d-94c0-4ef5c300c845 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520328320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.3520328320 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3054735202 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 130546100 ps |
CPU time | 2.5 seconds |
Started | May 23 03:35:06 PM PDT 24 |
Finished | May 23 03:35:11 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-e420910c-f20e-4d1d-8ae6-65cb7a00a815 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054735202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3054735202 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.767278166 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 410116582 ps |
CPU time | 8.15 seconds |
Started | May 23 03:35:11 PM PDT 24 |
Finished | May 23 03:35:25 PM PDT 24 |
Peak memory | 221452 kb |
Host | smart-028dcf63-1e4e-49c7-ba0a-a21d80003d36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767278166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.767278166 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1676785211 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 3515263805 ps |
CPU time | 73.81 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:36:44 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-a8e1f467-4e74-4a92-89c7-62d063e7265a |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676785211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.1676785211 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2570770388 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 2811723599 ps |
CPU time | 52.72 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:36:19 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-3235abe6-6fb9-4726-abf2-4209b20978fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570770388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2570770388 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3606128772 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 121903357 ps |
CPU time | 2.42 seconds |
Started | May 23 03:35:24 PM PDT 24 |
Finished | May 23 03:35:28 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-80c5027a-ad97-46f5-b6ba-e1256b4868cc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606128772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3606128772 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4201184721 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 136432851 ps |
CPU time | 2.74 seconds |
Started | May 23 03:35:32 PM PDT 24 |
Finished | May 23 03:35:37 PM PDT 24 |
Peak memory | 221276 kb |
Host | smart-cdc643a4-cc17-42a9-9576-9d3b4d1d7019 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201184721 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4201184721 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.374864918 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 73744433 ps |
CPU time | 1.61 seconds |
Started | May 23 03:35:24 PM PDT 24 |
Finished | May 23 03:35:27 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-a51a94ef-a278-49d0-995b-943e18f7b842 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374864918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.374864918 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2088546071 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 10850224530 ps |
CPU time | 43.67 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:36:10 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-8fdccfd5-4351-491e-b381-75a42017634d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088546071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2088546071 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1745442605 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 39532767478 ps |
CPU time | 61.62 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:36:33 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-d81fa22c-06f3-4ea2-9568-02e1641a5bd8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745442605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.1745442605 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.851969702 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 879412768 ps |
CPU time | 2.26 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:33 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-ad1cc79d-dda6-483f-b091-90169be7efe7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851969702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.851969702 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.175366072 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 99608539 ps |
CPU time | 0.75 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:29 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-5ec5a3ac-5cfd-411a-a599-78217c3555ac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175366072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _aliasing.175366072 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1433494651 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1161828842 ps |
CPU time | 2.64 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-21577bff-a3b6-463d-a27b-263c954e5c91 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433494651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1433494651 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1771663764 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 64705512 ps |
CPU time | 0.85 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:32 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-efcbb330-9037-419a-a7be-2d54d7901b03 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771663764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1771663764 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2649341028 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 144824198 ps |
CPU time | 0.97 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:35:28 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-33aa0a1b-2c3a-4162-b49f-359b3df00f47 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649341028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2 649341028 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1144183399 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 232739230 ps |
CPU time | 0.7 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:35:28 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-45a29cb3-43a7-41e1-8391-6e99c237676f |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144183399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1144183399 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2805315615 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 21510190 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:33 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-a9b22925-5c08-4f09-be29-33f4a40b4eb7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805315615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2805315615 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3855064386 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 3162664049 ps |
CPU time | 8.25 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-69a44f30-79b9-42cd-a183-70fa3ddd44d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855064386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3855064386 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2965680917 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 76194559 ps |
CPU time | 4.75 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:33 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-b502f4ec-8ba8-4165-b9c9-81775129f6cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965680917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2965680917 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3682585988 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 1789901864 ps |
CPU time | 4.1 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:35:44 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-2308c300-3d8c-4205-87c7-18c3629ea9e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682585988 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3682585988 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.440806140 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 300037502 ps |
CPU time | 2.1 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:45 PM PDT 24 |
Peak memory | 218652 kb |
Host | smart-13108da5-b0ec-492d-8eaa-d37a6bb69e35 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440806140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.440806140 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1659355604 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 815123074 ps |
CPU time | 1.37 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:46 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-10bc57e5-5d37-4367-888b-89a78a6c9756 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659355604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1659355604 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1454814999 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 38446642 ps |
CPU time | 0.74 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-a1033ced-62a6-4bc3-a943-e64b145cab0f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454814999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1454814999 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4091275919 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 413922069 ps |
CPU time | 4.24 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:53 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-1bed57c5-81b9-4647-b74f-8cb8a33e4c05 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091275919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.4091275919 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.3287874611 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 15897434475 ps |
CPU time | 13.67 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:36:02 PM PDT 24 |
Peak memory | 221608 kb |
Host | smart-f355649b-6667-4936-a2f5-ece263c85bb0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287874611 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.3287874611 |
Directory | /workspace/10.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3641068572 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 41604751 ps |
CPU time | 2.39 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-299c95d7-3163-4e73-822c-4176ed1a0959 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641068572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3641068572 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1786471770 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 880434584 ps |
CPU time | 9.08 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-5e6b4c12-5a32-4c72-a660-4aa94d67cd5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786471770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1 786471770 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.913820618 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 81783749 ps |
CPU time | 2.07 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:52 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-4e412f9b-0cfd-49a8-975b-576ee1714f88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913820618 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.913820618 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.371489346 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 408549093 ps |
CPU time | 2.4 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:53 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-73a05bad-7900-49d3-b7e8-0ed5a8f8ad52 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371489346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.371489346 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2525598453 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 178135223 ps |
CPU time | 1.04 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:49 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-6625878f-75be-414d-8fbd-6de1605a6a08 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525598453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 2525598453 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3147025359 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 145543808 ps |
CPU time | 1.06 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-8037ca1a-23ca-4d09-ab6f-8efd7d2c714a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147025359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3147025359 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.620002561 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 408845808 ps |
CPU time | 7.62 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:58 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-5c9945a0-475b-4951-852f-2cc4d80f77a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620002561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.620002561 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.130971556 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 30783840330 ps |
CPU time | 31.76 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:36:22 PM PDT 24 |
Peak memory | 221656 kb |
Host | smart-a537764b-4dff-498f-a519-4e93b024ae5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130971556 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.130971556 |
Directory | /workspace/11.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2927874063 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1322148824 ps |
CPU time | 19.41 seconds |
Started | May 23 03:35:48 PM PDT 24 |
Finished | May 23 03:36:12 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-47027188-edcb-4768-8d8b-005f0bd0a076 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927874063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2 927874063 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2175148267 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 88234829 ps |
CPU time | 2.18 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:45 PM PDT 24 |
Peak memory | 216604 kb |
Host | smart-235f5534-8efd-4e0a-b13f-5b8af6b6b1b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175148267 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2175148267 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2389310463 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 78454650 ps |
CPU time | 2.12 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 221452 kb |
Host | smart-6767d1f8-306f-4dbf-89c8-b67657324796 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389310463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2389310463 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3240687330 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 622161914 ps |
CPU time | 1.48 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:44 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-1be90f29-730d-4152-a765-895a65d28c67 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240687330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3240687330 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2365963349 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 61013371 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:45 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-a6148912-435b-4ce2-92cf-d2f60a694844 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365963349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 2365963349 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2944170358 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 233146159 ps |
CPU time | 6.53 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:35:47 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-4c939a6a-587d-4a48-97e0-3d6f38047500 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944170358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2944170358 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3331385832 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 14340343122 ps |
CPU time | 44.54 seconds |
Started | May 23 03:35:48 PM PDT 24 |
Finished | May 23 03:36:37 PM PDT 24 |
Peak memory | 221504 kb |
Host | smart-8fb9ab8d-b9d5-41d1-8875-53c066a20a01 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331385832 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.3331385832 |
Directory | /workspace/12.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.87963102 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 827407366 ps |
CPU time | 4.12 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:46 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-5c4236bf-a28c-481b-a1d4-68048a2c35fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87963102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.87963102 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.40896823 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 454181105 ps |
CPU time | 8.98 seconds |
Started | May 23 03:35:47 PM PDT 24 |
Finished | May 23 03:36:01 PM PDT 24 |
Peak memory | 221452 kb |
Host | smart-d058ff66-4c21-424c-8edc-d2411e5560f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.40896823 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.940461357 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 688075482 ps |
CPU time | 3.09 seconds |
Started | May 23 03:35:48 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 218060 kb |
Host | smart-21e68f40-c6a7-4566-81f6-9921e63266d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940461357 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.940461357 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2444002628 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 98855035 ps |
CPU time | 1.49 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:52 PM PDT 24 |
Peak memory | 221444 kb |
Host | smart-c9b9816f-66b9-4fc2-9f8c-3bd329205d73 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444002628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2444002628 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3418608423 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 838903849 ps |
CPU time | 2.34 seconds |
Started | May 23 03:35:48 PM PDT 24 |
Finished | May 23 03:35:55 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-c41ef02f-2564-4eb8-8c96-d4b1c0e3bae1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418608423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 3418608423 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3581766734 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 61235029 ps |
CPU time | 0.7 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-db4545c4-025a-4081-aa60-3f980997e529 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581766734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 3581766734 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2527415694 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 222786042 ps |
CPU time | 4 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:53 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-ec1742bb-0c3c-4ddd-8979-481fc26af441 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527415694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2527415694 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.824730771 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 585228307 ps |
CPU time | 4.38 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:52 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-725db8ba-0d32-44d6-bfd4-d7fe249abe36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824730771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.824730771 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.734712785 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 13053764199 ps |
CPU time | 18.62 seconds |
Started | May 23 03:35:48 PM PDT 24 |
Finished | May 23 03:36:11 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-91ea36dc-e7c1-4bd8-a60c-1e73f7a49947 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734712785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.734712785 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1301409255 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 618614071 ps |
CPU time | 3.56 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:53 PM PDT 24 |
Peak memory | 217556 kb |
Host | smart-eda0d06a-6c11-434d-a69b-4465483106f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301409255 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1301409255 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1825126257 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 203307986 ps |
CPU time | 1.55 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 218012 kb |
Host | smart-e8ceb62e-325d-4d62-9044-cdf7403dad45 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825126257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1825126257 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.231193449 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 463130012 ps |
CPU time | 1.61 seconds |
Started | May 23 03:35:49 PM PDT 24 |
Finished | May 23 03:35:55 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-0978ca54-e4a7-48b6-9cd9-a49959f67d33 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231193449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.231193449 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.155826714 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 42754668 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-5833b1b0-d8b6-47f6-87c3-ed57671b5c09 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155826714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.155826714 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1358149502 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 547708310 ps |
CPU time | 7.66 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:36:02 PM PDT 24 |
Peak memory | 204424 kb |
Host | smart-92807e8a-cdd6-4d82-b8d7-f43dc3e2fc1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358149502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.1358149502 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1416811222 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 228212049 ps |
CPU time | 3.16 seconds |
Started | May 23 03:35:49 PM PDT 24 |
Finished | May 23 03:35:57 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-e0f2d42d-1e8a-43b8-a467-457659bed862 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416811222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1416811222 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2463461339 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 115522506 ps |
CPU time | 2.26 seconds |
Started | May 23 03:35:51 PM PDT 24 |
Finished | May 23 03:35:57 PM PDT 24 |
Peak memory | 217024 kb |
Host | smart-a28f8253-9eca-4d3e-9fba-bbe3c8e5e3f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463461339 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2463461339 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4269878987 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 86398285 ps |
CPU time | 2.32 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 218784 kb |
Host | smart-cdc6740c-179b-41d6-8df5-d94884de8dba |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269878987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4269878987 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.972460999 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1510030608 ps |
CPU time | 1.4 seconds |
Started | May 23 03:35:51 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-47224ce8-6c11-451d-b54f-22b3e76ad4ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972460999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.972460999 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1468767190 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 22631603 ps |
CPU time | 0.78 seconds |
Started | May 23 03:35:49 PM PDT 24 |
Finished | May 23 03:35:54 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-3a39438d-2394-466c-9f2e-7b9bb7ea4c6f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468767190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 1468767190 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2886268704 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 304668014 ps |
CPU time | 6.49 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:49 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-fb6325e5-5265-4676-a01b-14372df80622 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886268704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.2886268704 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.771769266 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 168099721 ps |
CPU time | 4.96 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:35:59 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-dd5047e9-7e88-4c54-8b40-37e6176eb4ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771769266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.771769266 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1943896164 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 4152035266 ps |
CPU time | 5.26 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:36:00 PM PDT 24 |
Peak memory | 219092 kb |
Host | smart-af82c9da-3175-4506-9134-ef797b8e4a37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943896164 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1943896164 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1928878580 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 204118268 ps |
CPU time | 2.46 seconds |
Started | May 23 03:35:54 PM PDT 24 |
Finished | May 23 03:36:00 PM PDT 24 |
Peak memory | 219104 kb |
Host | smart-dd8d776b-0957-462e-851e-db6fc0a472bd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928878580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1928878580 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2897710360 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 2712653180 ps |
CPU time | 2.15 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:49 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-74a312bc-4cfa-4201-a3e6-4203737de8f4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897710360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2897710360 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1101477513 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 39016145 ps |
CPU time | 0.77 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-25d529ef-24a5-4e23-aeba-bf74649fcfe2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101477513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 1101477513 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2347228590 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 3392183412 ps |
CPU time | 8.14 seconds |
Started | May 23 03:35:49 PM PDT 24 |
Finished | May 23 03:36:02 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-fc411446-b90e-49c7-b6d5-6eb8996e9998 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347228590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2347228590 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.595079024 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1160873996 ps |
CPU time | 5.69 seconds |
Started | May 23 03:35:49 PM PDT 24 |
Finished | May 23 03:35:59 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-e56f7188-27b2-4ba1-bcc4-4c8c08c2a631 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595079024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.595079024 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1060924769 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 1484356417 ps |
CPU time | 19.21 seconds |
Started | May 23 03:35:54 PM PDT 24 |
Finished | May 23 03:36:17 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-4c876ffb-6316-4433-8efb-70de48ddf7a8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060924769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 060924769 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2341327974 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 2889555960 ps |
CPU time | 3.81 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 218616 kb |
Host | smart-8fcca097-10ab-4b87-bfda-c5dcbd8d567b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341327974 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2341327974 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3408183162 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 163733118 ps |
CPU time | 2.32 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-d05ff7dc-b759-4a5a-820a-aee55f9ede9b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408183162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3408183162 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2273529506 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 214159066 ps |
CPU time | 1.5 seconds |
Started | May 23 03:35:50 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-49778b35-5103-4a83-88a6-fc1c442315f2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273529506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 2273529506 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1698875245 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 23917288 ps |
CPU time | 0.76 seconds |
Started | May 23 03:35:51 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-92f9ee90-e953-465b-a054-a20604e48b95 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698875245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1698875245 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3866503990 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 208840194 ps |
CPU time | 3.94 seconds |
Started | May 23 03:35:48 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-aeb3ea77-670b-4155-af42-f5e264f4a8cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866503990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.3866503990 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1154997639 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 188148790 ps |
CPU time | 2.26 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 216744 kb |
Host | smart-2e9c84b5-f96f-4caa-9115-91f54f9463e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154997639 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1154997639 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2377248512 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 310460306 ps |
CPU time | 2.2 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:05 PM PDT 24 |
Peak memory | 221520 kb |
Host | smart-db367d9a-85cf-49e8-aaad-1a2972cd4e1f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377248512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2377248512 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.913650270 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 946420546 ps |
CPU time | 3.43 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:07 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-7dbd9577-e6b6-4db8-a05b-f7ba8996a475 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913650270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.913650270 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.844190386 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 54448335 ps |
CPU time | 0.74 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-5aaad08b-e79e-45a1-9be3-abe904363490 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844190386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.844190386 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.161182846 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 505517325 ps |
CPU time | 3.29 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:07 PM PDT 24 |
Peak memory | 215636 kb |
Host | smart-763a80c9-f7f9-418d-a010-dace3161c23e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161182846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.161182846 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2922105727 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 882719818 ps |
CPU time | 18.65 seconds |
Started | May 23 03:35:55 PM PDT 24 |
Finished | May 23 03:36:20 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-5cc8c1b9-8c98-44ea-9a95-ce595556ad65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922105727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2 922105727 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4170366566 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 2045893591 ps |
CPU time | 6.44 seconds |
Started | May 23 03:35:56 PM PDT 24 |
Finished | May 23 03:36:09 PM PDT 24 |
Peak memory | 217964 kb |
Host | smart-2bdebfd1-05a7-46d7-8dad-44b1ecb289ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170366566 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4170366566 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3386083044 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 124184441 ps |
CPU time | 2.4 seconds |
Started | May 23 03:35:54 PM PDT 24 |
Finished | May 23 03:36:00 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-f9fa7093-0697-489b-a2a5-944998903619 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386083044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3386083044 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.459649462 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 2698639241 ps |
CPU time | 9.19 seconds |
Started | May 23 03:35:58 PM PDT 24 |
Finished | May 23 03:36:14 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-b47b7c77-4612-4b2a-80a8-a65cf723d69d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459649462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.459649462 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3309581658 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 44435109 ps |
CPU time | 0.77 seconds |
Started | May 23 03:36:00 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-37f6ed26-e010-41e8-8631-dc5af7698e59 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309581658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 3309581658 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.440970048 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 127319720 ps |
CPU time | 3.61 seconds |
Started | May 23 03:35:55 PM PDT 24 |
Finished | May 23 03:36:03 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-ec8f892e-09b8-40bf-b5ea-64407fee5a97 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440970048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_ csr_outstanding.440970048 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.506018877 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 201263444 ps |
CPU time | 5.14 seconds |
Started | May 23 03:35:55 PM PDT 24 |
Finished | May 23 03:36:05 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-d9386346-16ed-49c9-8411-991d2fd3eb3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506018877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.506018877 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1493839718 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 3433346964 ps |
CPU time | 19.19 seconds |
Started | May 23 03:35:54 PM PDT 24 |
Finished | May 23 03:36:18 PM PDT 24 |
Peak memory | 221492 kb |
Host | smart-5415871b-954e-4500-908d-1f24a082b2b4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493839718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1 493839718 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.758080944 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 24443711968 ps |
CPU time | 39.43 seconds |
Started | May 23 03:35:24 PM PDT 24 |
Finished | May 23 03:36:05 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-311f2258-a7c1-4b67-b506-47f47ae15f78 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758080944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.rv_dm_csr_aliasing.758080944 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1634573156 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 7642603596 ps |
CPU time | 37.81 seconds |
Started | May 23 03:35:34 PM PDT 24 |
Finished | May 23 03:36:15 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-0b2548c5-f3c6-4d9b-97d1-76386fb4d51d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634573156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1634573156 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2562491904 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 217732339 ps |
CPU time | 2.37 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-aa457b22-80c2-4328-97e5-467c3959153a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562491904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2562491904 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3177007412 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 4250461219 ps |
CPU time | 6.2 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:35:38 PM PDT 24 |
Peak memory | 219228 kb |
Host | smart-e80f7099-df49-4ebc-b48d-a3ce5b2efe40 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177007412 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3177007412 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1829084449 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 56648690 ps |
CPU time | 1.56 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:34 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-eea6d32a-9f3d-4d23-be03-3b80e8aebc34 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829084449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1829084449 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.279291476 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 4973966942 ps |
CPU time | 21.12 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-a3029bfa-c58b-4657-afc0-825553dd5ec1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279291476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _aliasing.279291476 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3476041727 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 16324062176 ps |
CPU time | 25.78 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:55 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-f0e9e388-a76a-4dc7-8363-8d5f1f0342f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476041727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.3476041727 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2648219286 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 406017402 ps |
CPU time | 2.33 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:32 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-e3d0b528-21d5-4a1b-9b2f-5838f68c20ca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648219286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2 648219286 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3607502232 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 136005370 ps |
CPU time | 1.12 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:30 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-3d0ab211-d711-49dd-8b74-d1f138a63749 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607502232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.3607502232 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.789732064 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 481586945 ps |
CPU time | 2.6 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-eb3fb8b5-1f86-461a-9b16-758acaaf35f5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789732064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _bit_bash.789732064 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3002568210 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 170670541 ps |
CPU time | 0.84 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:35:27 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-59c41873-b22f-4bc4-8ddb-2de2e28d98d0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002568210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3002568210 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1950623600 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 66212409 ps |
CPU time | 0.72 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:31 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-4c9da2bd-6a0b-4dcb-8bcc-53a855c7885a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950623600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 950623600 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3682239349 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 53825111 ps |
CPU time | 0.69 seconds |
Started | May 23 03:35:25 PM PDT 24 |
Finished | May 23 03:35:28 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-613e0ac6-4076-4922-baf5-72e33066908c |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682239349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3682239349 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2333857151 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 18345613 ps |
CPU time | 0.7 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:31 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-4d4eea64-9d89-4756-b908-5245f08a1f3d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333857151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2333857151 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2452940274 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 313908276 ps |
CPU time | 3.82 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:36 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-f382a697-1180-440f-aab5-364e2bdca0d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452940274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.2452940274 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1969592465 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 214448896 ps |
CPU time | 5.25 seconds |
Started | May 23 03:35:34 PM PDT 24 |
Finished | May 23 03:35:42 PM PDT 24 |
Peak memory | 213052 kb |
Host | smart-528b57cc-37df-45aa-8837-eadf4a1f0f6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969592465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1969592465 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1760662098 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 1495334694 ps |
CPU time | 9.62 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:39 PM PDT 24 |
Peak memory | 221380 kb |
Host | smart-a1e9f374-ba8b-4e53-bbee-8102b7edb5d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760662098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1760662098 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.3627419423 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 26584536375 ps |
CPU time | 27.89 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:31 PM PDT 24 |
Peak memory | 221660 kb |
Host | smart-3100ac8d-1629-4880-a693-a4aa2c96ed39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627419423 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.3627419423 |
Directory | /workspace/23.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.3136747755 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 7466086207 ps |
CPU time | 26.45 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:30 PM PDT 24 |
Peak memory | 221524 kb |
Host | smart-3651d3ca-a38b-4d54-afbc-9459ac21e354 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136747755 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.3136747755 |
Directory | /workspace/26.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2634863680 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 7954448968 ps |
CPU time | 27.63 seconds |
Started | May 23 03:35:55 PM PDT 24 |
Finished | May 23 03:36:27 PM PDT 24 |
Peak memory | 214672 kb |
Host | smart-72cfa691-617c-4b89-85a7-0ffb6c9f8150 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634863680 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2634863680 |
Directory | /workspace/27.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2978141022 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 20373051728 ps |
CPU time | 65.45 seconds |
Started | May 23 03:36:00 PM PDT 24 |
Finished | May 23 03:37:11 PM PDT 24 |
Peak memory | 221668 kb |
Host | smart-4ee9aec0-6c5c-42b8-88fe-5a7be7f73915 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978141022 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.2978141022 |
Directory | /workspace/28.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2559764545 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3400996145 ps |
CPU time | 74.13 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:36:45 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-af908c14-e30e-4a31-b771-06008ac22ef8 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559764545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.2559764545 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1231053167 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 19624383065 ps |
CPU time | 71.65 seconds |
Started | May 23 03:35:31 PM PDT 24 |
Finished | May 23 03:36:46 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-c73e003a-46b6-40b2-a308-c670fcfe13a7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231053167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1231053167 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3817226216 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 186152058 ps |
CPU time | 2.43 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-a8d50a9a-f246-4f40-a474-c469c8da5129 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817226216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3817226216 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2635224542 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 4957039858 ps |
CPU time | 21.73 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:53 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-8237dcb2-cc12-4207-8e49-8625686d6657 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635224542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.2635224542 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1933576719 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 8341223711 ps |
CPU time | 35.22 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:36:06 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-20028dfe-f233-4e3f-bef8-5ae916432d1e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933576719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.1933576719 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3437480250 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 927485328 ps |
CPU time | 1.95 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:35:33 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-df228ae7-e806-4c64-a7f8-1440de7106d8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437480250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.3437480250 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.319251788 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 424513254 ps |
CPU time | 1.68 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:32 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-a0615739-5374-4ac9-9e8a-6b34fb47c2e3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319251788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.319251788 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1227541101 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 99641235 ps |
CPU time | 0.75 seconds |
Started | May 23 03:35:34 PM PDT 24 |
Finished | May 23 03:35:38 PM PDT 24 |
Peak memory | 204812 kb |
Host | smart-2d27ef57-3098-4a16-b369-3bec853696f1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227541101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.1227541101 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1695393315 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 661293452 ps |
CPU time | 3.17 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-295ce774-cbcf-4739-bee1-b4076b1a4e25 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695393315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1695393315 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4163075742 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 41086899 ps |
CPU time | 0.79 seconds |
Started | May 23 03:35:26 PM PDT 24 |
Finished | May 23 03:35:30 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-a67038c8-ecce-4e0b-8803-dea67f65cd6a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163075742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.4163075742 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.538713903 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 201990004 ps |
CPU time | 0.77 seconds |
Started | May 23 03:35:32 PM PDT 24 |
Finished | May 23 03:35:36 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-11c3821e-f678-45f1-a293-f78c5b87e698 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538713903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.538713903 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4052935823 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 24455699 ps |
CPU time | 0.68 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:32 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-618c85a7-e3af-4b87-b22a-1b7ad5cb8047 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052935823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.4052935823 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3361757359 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 29251305 ps |
CPU time | 0.71 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:32 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-18607657-28f7-4ed6-b105-78ce65f9ada0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361757359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3361757359 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.897383230 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 93349532 ps |
CPU time | 3.68 seconds |
Started | May 23 03:35:34 PM PDT 24 |
Finished | May 23 03:35:40 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-11a3d57f-ebf1-4330-b5f5-b283d329e4d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897383230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c sr_outstanding.897383230 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4219742295 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 228473709 ps |
CPU time | 2.7 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-5ad4d040-d5be-4b09-9761-f64945c2d017 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219742295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4219742295 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.1497113946 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 14310754490 ps |
CPU time | 13.56 seconds |
Started | May 23 03:35:57 PM PDT 24 |
Finished | May 23 03:36:17 PM PDT 24 |
Peak memory | 218960 kb |
Host | smart-4db8b3e9-d4d7-4d72-a682-e4762d9e3af3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497113946 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.1497113946 |
Directory | /workspace/37.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.730090323 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 7971164007 ps |
CPU time | 75.06 seconds |
Started | May 23 03:35:31 PM PDT 24 |
Finished | May 23 03:36:49 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-dde51e5c-956d-4874-9106-808f08ad8b21 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730090323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.rv_dm_csr_aliasing.730090323 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3162372337 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 4908460114 ps |
CPU time | 66.78 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:36:52 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-f80b902b-47d2-46a8-91c3-c4e901109a2a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162372337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3162372337 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3367839721 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 183003616 ps |
CPU time | 1.62 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-d99b60a1-40a5-4dd3-88b5-a85caaf34fd4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367839721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3367839721 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3058425551 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 1391654954 ps |
CPU time | 5.01 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:54 PM PDT 24 |
Peak memory | 218316 kb |
Host | smart-d618c3ed-6c4e-48a5-8394-baa96143eb00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058425551 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3058425551 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2792950165 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 89097364 ps |
CPU time | 1.43 seconds |
Started | May 23 03:35:35 PM PDT 24 |
Finished | May 23 03:35:38 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-7df6b8c6-c3b3-4787-a84c-78ff09d8f773 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792950165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2792950165 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3402047318 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 3308823216 ps |
CPU time | 10.87 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:35:43 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-c9ec846b-095c-4853-b472-e217a6321eb3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402047318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3402047318 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.180888793 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 54359552938 ps |
CPU time | 106.06 seconds |
Started | May 23 03:35:28 PM PDT 24 |
Finished | May 23 03:37:18 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-7e8cc207-c75d-4d06-84b5-78d14a1d351a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180888793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.180888793 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.330818360 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 457649493 ps |
CPU time | 2.06 seconds |
Started | May 23 03:35:34 PM PDT 24 |
Finished | May 23 03:35:39 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-877a537b-b733-4cb6-bc78-8d2451ab8110 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330818360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.330818360 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1655522352 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 105993889 ps |
CPU time | 0.96 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:33 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-d20984bc-08a0-4375-804a-69486953c3d4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655522352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.1655522352 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3646242870 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 1746183809 ps |
CPU time | 1.43 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:34 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-842a9265-cf78-4d09-b24a-0129a98eb4b6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646242870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.3646242870 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3406454261 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 39213413 ps |
CPU time | 0.76 seconds |
Started | May 23 03:35:29 PM PDT 24 |
Finished | May 23 03:35:33 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-a4d1a968-5848-43be-b685-11320d926f9d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406454261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.3406454261 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1064138406 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 70111489 ps |
CPU time | 0.82 seconds |
Started | May 23 03:35:32 PM PDT 24 |
Finished | May 23 03:35:35 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-d288cd0f-cfb5-4fef-a80a-5b9214c97591 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064138406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 064138406 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1532073899 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 43732922 ps |
CPU time | 0.7 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-364dfcd9-1c32-4292-9491-5682b050e065 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532073899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1532073899 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3956100858 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 79400181 ps |
CPU time | 0.73 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-93c70f69-2d7d-4dd3-ac59-ac620a90d6e5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956100858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3956100858 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.281795516 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 535074369 ps |
CPU time | 7.93 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-4a91bc8b-1b3f-4a10-a0c7-894f720687ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281795516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c sr_outstanding.281795516 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.877381116 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 159745483 ps |
CPU time | 4.15 seconds |
Started | May 23 03:35:32 PM PDT 24 |
Finished | May 23 03:35:39 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-5890443a-8195-405f-8218-b85db969a487 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877381116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.877381116 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.329118951 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 978545781 ps |
CPU time | 8.1 seconds |
Started | May 23 03:35:27 PM PDT 24 |
Finished | May 23 03:35:39 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-0f334687-285b-4c65-9af6-79b2886e0860 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329118951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.329118951 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3185059527 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 3585005294 ps |
CPU time | 7.19 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:55 PM PDT 24 |
Peak memory | 217140 kb |
Host | smart-ec67a30d-3432-4320-bb2f-56640295bfdc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185059527 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3185059527 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3616142775 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 168725122 ps |
CPU time | 2.18 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 219124 kb |
Host | smart-b42128c6-a078-45bb-b81e-1936a78d7082 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616142775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3616142775 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.433270639 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 882893452 ps |
CPU time | 1.89 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-c134e776-1014-4143-a1c7-f1fdf0076825 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433270639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.433270639 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4210504391 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 103089524 ps |
CPU time | 0.72 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:46 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-834a8520-d445-450c-8ecf-ef1af9cf93de |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210504391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4 210504391 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3425786714 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 159910225 ps |
CPU time | 6.37 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:55 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-524321b0-63d7-4c2f-b008-2b35992cadbc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425786714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3425786714 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3582349674 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 161818478 ps |
CPU time | 2.55 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-3aa704d4-692a-4899-96ad-87d837f197f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582349674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3582349674 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1944513147 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 1904075365 ps |
CPU time | 4.04 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:35:45 PM PDT 24 |
Peak memory | 221460 kb |
Host | smart-9e6c49c1-203a-4637-b240-2dcf68d65863 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944513147 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1944513147 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1509771324 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 426854988 ps |
CPU time | 2.38 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 219024 kb |
Host | smart-bda7b52a-8774-45ef-bac9-d133d47b60ae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509771324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1509771324 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.975556697 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 182069702 ps |
CPU time | 1.49 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:43 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-406c0190-c8fa-4fe9-a18a-8373a4ca50bd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975556697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.975556697 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.268035570 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 115384320 ps |
CPU time | 0.77 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:44 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-123b6af4-4703-45b8-bafe-d8743c1b7489 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268035570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.268035570 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.936526542 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 162555493 ps |
CPU time | 6.38 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:35:47 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-62f9262e-1f98-42c0-8e47-91c44bdb077a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936526542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.936526542 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1439555902 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 945394860 ps |
CPU time | 5.74 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:35:46 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-b5177a12-9be0-4e9a-a5d0-c4ae8f7e36a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439555902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1439555902 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2974731779 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 2088864102 ps |
CPU time | 9.93 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:56 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-49188b65-2486-4931-bd07-0c5b9a6756e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974731779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2974731779 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3330280044 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 2476609298 ps |
CPU time | 4.23 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 216284 kb |
Host | smart-4c71d36a-ca7e-4e49-8e4c-48a0c1ba5591 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330280044 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3330280044 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2917389512 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 970278528 ps |
CPU time | 3.88 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-b8c91c73-8d4d-4b1a-961c-a9ca79d68f3b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917389512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2 917389512 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2271192692 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 516897002 ps |
CPU time | 4.66 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-2754bbd0-c5de-4577-9e30-892e0f73dc50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271192692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.2271192692 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.146055772 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 23179986955 ps |
CPU time | 12.66 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:36:01 PM PDT 24 |
Peak memory | 216468 kb |
Host | smart-5cea91ca-eaeb-4c69-8e68-f0f06f29802d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146055772 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.146055772 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1988016850 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 72993244 ps |
CPU time | 2.24 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:49 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-075501c4-5012-4ec9-849b-3b992e5ef719 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988016850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1988016850 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2252266552 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 944227376 ps |
CPU time | 9.85 seconds |
Started | May 23 03:35:40 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-958cf5bd-67da-49e3-8aa1-57456dc96e39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252266552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2252266552 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3685531568 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 65315592 ps |
CPU time | 2.71 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:52 PM PDT 24 |
Peak memory | 219184 kb |
Host | smart-f9e851d4-3035-444c-9907-8010e9f1a74e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685531568 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3685531568 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3133124050 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 639328840 ps |
CPU time | 2.06 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:35:43 PM PDT 24 |
Peak memory | 218772 kb |
Host | smart-2fce74a4-ca5a-4071-99eb-2d3aca88767f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133124050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3133124050 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.679456851 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 590770756 ps |
CPU time | 2.83 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-2afde432-63c5-43fd-85ba-e39357413688 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679456851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.679456851 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1047914286 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 36276977 ps |
CPU time | 0.75 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:47 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-e3339514-82ee-42a1-923c-6dfd2f069be5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047914286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1 047914286 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3280167380 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 300978930 ps |
CPU time | 3.62 seconds |
Started | May 23 03:35:41 PM PDT 24 |
Finished | May 23 03:35:46 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-4bbe95ec-80a9-4880-9e23-d9c061410dd5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280167380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3280167380 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2269170036 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 636510006 ps |
CPU time | 8.66 seconds |
Started | May 23 03:35:40 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 221384 kb |
Host | smart-89be6a82-7baa-48ab-bd3e-5a3aa0dbcf14 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269170036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2269170036 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3555971166 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 467467433 ps |
CPU time | 3.74 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 217792 kb |
Host | smart-d3c7d444-f377-458a-9146-c548952ba73b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555971166 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3555971166 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1762378772 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 80043876 ps |
CPU time | 2.05 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 221528 kb |
Host | smart-28ed4b4b-7bb5-4709-8945-3bbd20a6738a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762378772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1762378772 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.138744180 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 401693609 ps |
CPU time | 1.57 seconds |
Started | May 23 03:35:45 PM PDT 24 |
Finished | May 23 03:35:51 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-839c129b-e628-497e-9796-f39aeb3e90cb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138744180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.138744180 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1827935064 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 28323228 ps |
CPU time | 0.76 seconds |
Started | May 23 03:35:43 PM PDT 24 |
Finished | May 23 03:35:48 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-65556b49-2ff5-43f0-91a1-e5fc199599a6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827935064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 827935064 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.264209452 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 286645177 ps |
CPU time | 6.25 seconds |
Started | May 23 03:35:44 PM PDT 24 |
Finished | May 23 03:35:55 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-f498ccba-ff74-4ed8-9575-4854b4d26e35 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264209452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.264209452 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1119929767 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 118104724 ps |
CPU time | 3.65 seconds |
Started | May 23 03:35:42 PM PDT 24 |
Finished | May 23 03:35:50 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-88a202c1-c307-46c1-b52c-77b5d98a3067 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119929767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1119929767 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.398605460 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 2208102086 ps |
CPU time | 19.93 seconds |
Started | May 23 03:35:39 PM PDT 24 |
Finished | May 23 03:36:00 PM PDT 24 |
Peak memory | 221556 kb |
Host | smart-e25c01f5-7c2c-40b1-b693-ac742e7c66bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398605460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.398605460 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2085763368 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 38579829 ps |
CPU time | 0.77 seconds |
Started | May 23 03:30:37 PM PDT 24 |
Finished | May 23 03:30:40 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-03444836-0d8b-4ced-bf4c-9f87bd3b2878 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085763368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2085763368 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.2846264590 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 68291864 ps |
CPU time | 0.74 seconds |
Started | May 23 03:30:33 PM PDT 24 |
Finished | May 23 03:30:37 PM PDT 24 |
Peak memory | 212952 kb |
Host | smart-fc07f288-89db-4d85-ac1a-3e80b4849984 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846264590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2846264590 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2770823818 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 560720265 ps |
CPU time | 1.24 seconds |
Started | May 23 03:30:33 PM PDT 24 |
Finished | May 23 03:30:37 PM PDT 24 |
Peak memory | 228832 kb |
Host | smart-09dcd61a-772b-478c-84ab-d5f4f8bfe017 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770823818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2770823818 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.310467147 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 882747496 ps |
CPU time | 3.36 seconds |
Started | May 23 03:30:34 PM PDT 24 |
Finished | May 23 03:30:41 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-fe3536b2-db35-4f0a-84d1-4601f3f64536 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310467147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.310467147 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1751793199 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 104019989 ps |
CPU time | 0.72 seconds |
Started | May 23 03:30:45 PM PDT 24 |
Finished | May 23 03:30:48 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-00bf7a31-8631-45dd-b727-675ed70ddb50 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751793199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1751793199 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.792649618 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 152179230 ps |
CPU time | 0.68 seconds |
Started | May 23 03:30:53 PM PDT 24 |
Finished | May 23 03:30:55 PM PDT 24 |
Peak memory | 204556 kb |
Host | smart-fd9ffc8d-3d1e-4ef8-b76c-50f3f839c89d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792649618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.792649618 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.79789007 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 163947789 ps |
CPU time | 0.96 seconds |
Started | May 23 03:30:45 PM PDT 24 |
Finished | May 23 03:30:48 PM PDT 24 |
Peak memory | 229440 kb |
Host | smart-32166240-7e42-4469-a3db-6e3888c2067e |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79789007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.79789007 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.3172795613 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 649705956 ps |
CPU time | 1.3 seconds |
Started | May 23 03:30:34 PM PDT 24 |
Finished | May 23 03:30:38 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-84d17775-ad92-4c2c-8bf5-93495606bed5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172795613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3172795613 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1621275092 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 14575431 ps |
CPU time | 0.69 seconds |
Started | May 23 03:31:21 PM PDT 24 |
Finished | May 23 03:31:24 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-e85f1cf4-4903-4f82-9cab-d982b42f9b37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621275092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1621275092 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.4083213254 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2313005940 ps |
CPU time | 5.36 seconds |
Started | May 23 03:31:23 PM PDT 24 |
Finished | May 23 03:31:31 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-88a21013-c1d7-47e5-a4d7-9de520bfe4a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083213254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4083213254 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.3030482471 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 64991236 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:20 PM PDT 24 |
Finished | May 23 03:31:23 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-a1320597-4d01-46e4-b960-c521ff10fe8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030482471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3030482471 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.3777808356 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 19535404 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:25 PM PDT 24 |
Finished | May 23 03:31:29 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-cd2c6669-04bc-4ea4-b293-4da0aedff61b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777808356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3777808356 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1338939377 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 16950452 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:20 PM PDT 24 |
Finished | May 23 03:31:22 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-3646a473-805a-42a7-a4b6-4df10fc88d48 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338939377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1338939377 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.483733805 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 40364004 ps |
CPU time | 0.69 seconds |
Started | May 23 03:31:22 PM PDT 24 |
Finished | May 23 03:31:25 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-2614a4fc-c735-48d3-85b5-7118e7f6fb04 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483733805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.483733805 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.4146288252 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 3582369582 ps |
CPU time | 12.89 seconds |
Started | May 23 03:31:23 PM PDT 24 |
Finished | May 23 03:31:39 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-01e37e90-a67a-43a9-89d5-729df637638c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146288252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.4146288252 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1027514857 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 38278907 ps |
CPU time | 0.75 seconds |
Started | May 23 03:31:24 PM PDT 24 |
Finished | May 23 03:31:28 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-d8ca2483-0f4b-4d10-9ccb-16c67aaf1b2b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027514857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1027514857 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.1425203537 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 57338241 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:24 PM PDT 24 |
Finished | May 23 03:31:27 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-f7bc2296-91ae-419e-83f7-efb692c0fbfb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425203537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1425203537 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.590072548 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 17688162 ps |
CPU time | 0.69 seconds |
Started | May 23 03:31:41 PM PDT 24 |
Finished | May 23 03:31:45 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-26e1ed9b-61c2-4bd1-a4a2-a10b1ba7b5e9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590072548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.590072548 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.2355149213 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 51830206 ps |
CPU time | 0.7 seconds |
Started | May 23 03:30:46 PM PDT 24 |
Finished | May 23 03:30:50 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-0202d928-52cc-4ecb-a7f9-7009931081f6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355149213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2355149213 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.869883075 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 365898017 ps |
CPU time | 1.38 seconds |
Started | May 23 03:30:48 PM PDT 24 |
Finished | May 23 03:30:52 PM PDT 24 |
Peak memory | 229108 kb |
Host | smart-35567810-bbd1-4bc5-9301-05cc950f195a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869883075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.869883075 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2102836087 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 43386979 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:46 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-6a139a56-f678-4403-be94-0cbf421d9558 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102836087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2102836087 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.3196334037 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 30789749 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:47 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-75238987-3564-4a47-9e80-c81241f12094 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196334037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3196334037 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.1116329017 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 3722221589 ps |
CPU time | 3.93 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:50 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-7ffde190-a78f-4e07-8107-169a84f9d7ff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116329017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1116329017 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.1517334360 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 32614204 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:47 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-170aef16-9a35-4141-9360-c827cee778d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517334360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1517334360 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3612333771 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 40527739 ps |
CPU time | 0.66 seconds |
Started | May 23 03:31:41 PM PDT 24 |
Finished | May 23 03:31:44 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-f1fd6626-1322-4085-b27e-07b08da46d54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612333771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3612333771 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.284650890 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 56055370 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:43 PM PDT 24 |
Finished | May 23 03:31:48 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-c34a5ca9-b851-4abd-9b3e-7a706168d11d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284650890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.284650890 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1341935184 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 37223394 ps |
CPU time | 0.74 seconds |
Started | May 23 03:31:40 PM PDT 24 |
Finished | May 23 03:31:42 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-87c60dfa-741f-4ede-8db0-547425dac8e7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341935184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1341935184 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2554250039 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 40998960 ps |
CPU time | 0.7 seconds |
Started | May 23 03:31:40 PM PDT 24 |
Finished | May 23 03:31:43 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-905139ec-9c82-4c30-8ee0-1fc1cf042879 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554250039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2554250039 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.2668291742 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 22949913 ps |
CPU time | 0.73 seconds |
Started | May 23 03:31:41 PM PDT 24 |
Finished | May 23 03:31:45 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-a86b5caa-9a16-4d93-8711-f047702522d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668291742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2668291742 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2617092867 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 83442842 ps |
CPU time | 0.74 seconds |
Started | May 23 03:31:44 PM PDT 24 |
Finished | May 23 03:31:49 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-0948b026-dfef-4864-b69d-fe1a384bdca7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617092867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2617092867 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.3938703663 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1883776491 ps |
CPU time | 6.87 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:52 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-5366354c-234f-4894-acb3-f402fa095632 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938703663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3938703663 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.1932307291 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 19338407 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:41 PM PDT 24 |
Finished | May 23 03:31:44 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-93bec60b-50d2-4ec1-b02d-481d46cbf48a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932307291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1932307291 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.3665100474 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 6920191184 ps |
CPU time | 6.8 seconds |
Started | May 23 03:31:45 PM PDT 24 |
Finished | May 23 03:31:56 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-aae322da-904b-452c-94f0-5f39f20d503d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665100474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3665100474 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.1497316247 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 27039422 ps |
CPU time | 0.72 seconds |
Started | May 23 03:30:51 PM PDT 24 |
Finished | May 23 03:30:54 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-19f07302-517a-4388-b6e4-224948fa65cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497316247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1497316247 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.476379670 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 54701993 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:46 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-4d642b5b-6c3b-4983-a6d8-88cc06565354 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476379670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.476379670 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1978843855 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 22322544 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:43 PM PDT 24 |
Finished | May 23 03:31:48 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-645c7be6-e353-4505-8bc3-9d22de318bf8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978843855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1978843855 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.781249593 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 68568943 ps |
CPU time | 0.73 seconds |
Started | May 23 03:31:43 PM PDT 24 |
Finished | May 23 03:31:47 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-3b1144ee-1816-423e-a569-9e2f4b2c1fc0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781249593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.781249593 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1556736023 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 26171826 ps |
CPU time | 0.7 seconds |
Started | May 23 03:31:45 PM PDT 24 |
Finished | May 23 03:31:50 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-7519cf0d-57e0-41b5-9726-4fcef59ab5f1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556736023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1556736023 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.2064266321 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 178695707 ps |
CPU time | 0.73 seconds |
Started | May 23 03:31:42 PM PDT 24 |
Finished | May 23 03:31:47 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-43ac71d6-ca4d-49f1-a452-ab5d86d24ca1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064266321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2064266321 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.2238757631 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 58350521 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:48 PM PDT 24 |
Finished | May 23 03:31:53 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-251e346e-4329-469b-9adc-530dbf1e211e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238757631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2238757631 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.1080989097 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 30417670 ps |
CPU time | 0.7 seconds |
Started | May 23 03:31:43 PM PDT 24 |
Finished | May 23 03:31:48 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-ac4a5ce0-56b6-4e65-a720-003647099b58 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080989097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1080989097 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2992327531 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 53150362 ps |
CPU time | 0.68 seconds |
Started | May 23 03:31:43 PM PDT 24 |
Finished | May 23 03:31:47 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-26dffe4e-3423-4e01-806b-11320029ab71 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992327531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2992327531 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1038061355 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 28670119 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:45 PM PDT 24 |
Finished | May 23 03:31:50 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-d612e416-f0c9-46cd-bc75-df74806326b5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038061355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1038061355 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.1609092877 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 18787069 ps |
CPU time | 0.69 seconds |
Started | May 23 03:31:45 PM PDT 24 |
Finished | May 23 03:31:49 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-355330e4-4a5f-45f1-a64d-28c87aa5ff4a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609092877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1609092877 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.732295839 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 29206702 ps |
CPU time | 0.74 seconds |
Started | May 23 03:30:58 PM PDT 24 |
Finished | May 23 03:31:02 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-f6a0488f-75ea-448a-9ce8-2d061d72373d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732295839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.732295839 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.4154085446 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 621186551 ps |
CPU time | 1.33 seconds |
Started | May 23 03:30:57 PM PDT 24 |
Finished | May 23 03:31:01 PM PDT 24 |
Peak memory | 229080 kb |
Host | smart-9efa9db8-838d-4420-ac8f-2d2a2dd21c84 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154085446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4154085446 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.4199230538 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 51932490 ps |
CPU time | 0.73 seconds |
Started | May 23 03:31:45 PM PDT 24 |
Finished | May 23 03:31:50 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-5af3ab49-d880-40df-9128-0ad4cb6ea144 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199230538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4199230538 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.4082141893 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 37248019 ps |
CPU time | 0.75 seconds |
Started | May 23 03:31:47 PM PDT 24 |
Finished | May 23 03:31:51 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-b15b1f1d-10c0-4320-a6fd-e1c1ccf65dda |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082141893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4082141893 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3212994189 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 51396048 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:46 PM PDT 24 |
Finished | May 23 03:31:50 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-64610c71-a94d-4f00-95ca-bc26ba210eea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212994189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3212994189 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.3735888622 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 35206178 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:47 PM PDT 24 |
Finished | May 23 03:31:52 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-f34740b3-1d15-4580-89a7-942e4d7338f3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735888622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3735888622 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.227437926 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 30313844 ps |
CPU time | 0.75 seconds |
Started | May 23 03:31:46 PM PDT 24 |
Finished | May 23 03:31:51 PM PDT 24 |
Peak memory | 204660 kb |
Host | smart-c9ab95b2-e28c-46cf-9204-640e160bdc31 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227437926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.227437926 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3948124115 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 18529250 ps |
CPU time | 0.72 seconds |
Started | May 23 03:31:48 PM PDT 24 |
Finished | May 23 03:31:52 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-cd65e15a-17c8-4dc2-9f6e-9bb665a510ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948124115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3948124115 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.2547226830 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 1987929503 ps |
CPU time | 3.92 seconds |
Started | May 23 03:31:47 PM PDT 24 |
Finished | May 23 03:31:55 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-3108517d-975f-4fed-8467-9f7fab3780c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547226830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2547226830 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3460701562 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 27582941 ps |
CPU time | 0.66 seconds |
Started | May 23 03:31:48 PM PDT 24 |
Finished | May 23 03:31:52 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-b2eb8ec9-bb38-4e33-bb0e-053b9618879d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460701562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3460701562 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.975537193 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 18863716 ps |
CPU time | 0.69 seconds |
Started | May 23 03:31:46 PM PDT 24 |
Finished | May 23 03:31:51 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-88711aa3-fc82-404f-991e-745f0f60cee4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975537193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.975537193 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.1799207636 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 15689776 ps |
CPU time | 0.69 seconds |
Started | May 23 03:32:05 PM PDT 24 |
Finished | May 23 03:32:08 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-c2513f13-2c6a-45a3-817f-4fc02f7b2afe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799207636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1799207636 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1487587254 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 56878089 ps |
CPU time | 0.68 seconds |
Started | May 23 03:31:52 PM PDT 24 |
Finished | May 23 03:31:54 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-1762abb8-e3a7-466b-ab7d-603f45c5c57b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487587254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1487587254 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.2767871024 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 41757526 ps |
CPU time | 0.76 seconds |
Started | May 23 03:30:58 PM PDT 24 |
Finished | May 23 03:31:03 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-1455089e-13b8-4500-8200-7dade893f567 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767871024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2767871024 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.729380241 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 2259950065 ps |
CPU time | 4.57 seconds |
Started | May 23 03:30:57 PM PDT 24 |
Finished | May 23 03:31:04 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-bd7691fd-ed27-4702-b844-91025d760b89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729380241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.729380241 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.2437374839 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 103757207 ps |
CPU time | 0.72 seconds |
Started | May 23 03:30:59 PM PDT 24 |
Finished | May 23 03:31:03 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-97bc9d34-7f13-4f7e-909c-724780fde91c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437374839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2437374839 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.1426095234 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 26510383 ps |
CPU time | 0.7 seconds |
Started | May 23 03:30:57 PM PDT 24 |
Finished | May 23 03:31:00 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-d327869f-f085-4ce4-9e99-47c29d15bd96 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426095234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1426095234 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.3796573662 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 47951105 ps |
CPU time | 0.71 seconds |
Started | May 23 03:31:20 PM PDT 24 |
Finished | May 23 03:31:22 PM PDT 24 |
Peak memory | 204536 kb |
Host | smart-93b76db9-1eff-4e22-8c0a-4850a0c558fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796573662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3796573662 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.3383981045 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 22741609 ps |
CPU time | 0.69 seconds |
Started | May 23 03:31:22 PM PDT 24 |
Finished | May 23 03:31:25 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-b06a32d5-e02a-430c-a0ca-c037ab35683f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383981045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3383981045 |
Directory | /workspace/9.rv_dm_alert_test/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |