Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	191691	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	529377	1		T5	39		T6	37		T7	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	460794	1		T5	8		T6	14		T7	8
values[0x0]	128842	1		T5	55		T6	43		T8	29
values[0x1]	131432	1		T5	58		T6	41		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146344	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	574724	1		T5	47		T6	44		T7	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3014	1		T5	1		T6	98		T66	7
valid_sources[0x01]	2973	1		T5	2		T27	5		T29	17
valid_sources[0x02]	2401	1		T5	1		T31	3		T27	2
valid_sources[0x03]	2500	1		T11	2		T14	4		T12	1
valid_sources[0x04]	2736	1		T12	2		T31	6		T27	4
valid_sources[0x05]	4502	1		T8	1		T31	6		T27	2
valid_sources[0x06]	3436	1		T9	1		T31	2		T27	2
valid_sources[0x07]	2560	1		T15	11		T9	3		T31	3
valid_sources[0x08]	2490	1		T27	3		T29	3		T28	2
valid_sources[0x09]	2542	1		T31	7		T27	2		T29	10
valid_sources[0x0a]	2554	1		T31	14		T27	3		T29	9
valid_sources[0x0b]	2541	1		T5	1		T31	7		T27	3
valid_sources[0x0c]	2893	1		T31	9		T27	2		T75	2
valid_sources[0x0d]	2849	1		T9	1		T31	11		T27	2
valid_sources[0x0e]	2814	1		T8	1		T14	1		T31	3
valid_sources[0x0f]	2515	1		T5	2		T66	1		T27	5
valid_sources[0x10]	2704	1		T14	1		T31	5		T27	3
valid_sources[0x11]	2514	1		T5	1		T31	8		T27	7
valid_sources[0x12]	2672	1		T31	2		T27	5		T29	20
valid_sources[0x13]	2975	1		T31	6		T29	10		T28	3
valid_sources[0x14]	3133	1		T8	1		T15	6		T31	8
valid_sources[0x15]	2482	1		T5	1		T9	1		T31	1
valid_sources[0x16]	2812	1		T31	3		T27	7		T29	7
valid_sources[0x17]	3589	1		T31	7		T27	3		T75	40
valid_sources[0x18]	2699	1		T11	1		T9	1		T31	11
valid_sources[0x19]	2633	1		T5	4		T12	1		T31	2
valid_sources[0x1a]	2350	1		T14	1		T9	1		T31	6
valid_sources[0x1b]	2807	1		T5	1		T27	4		T29	14
valid_sources[0x1c]	3257	1		T8	1		T14	4		T9	2
valid_sources[0x1d]	2594	1		T8	2		T31	1		T29	6
valid_sources[0x1e]	2592	1		T14	3		T15	1		T31	1
valid_sources[0x1f]	2748	1		T9	2		T31	4		T27	4
valid_sources[0x20]	2779	1		T9	1		T31	2		T27	5
valid_sources[0x21]	2591	1		T31	3		T27	4		T29	8
valid_sources[0x22]	2602	1		T14	1		T12	5		T23	5
valid_sources[0x23]	2339	1		T5	1		T14	2		T31	6
valid_sources[0x24]	2388	1		T31	3		T27	3		T29	17
valid_sources[0x25]	2691	1		T9	1		T31	6		T27	4
valid_sources[0x26]	2773	1		T31	24		T27	2		T29	12
valid_sources[0x27]	2732	1		T31	5		T27	3		T29	15
valid_sources[0x28]	2636	1		T66	6		T31	2		T27	4
valid_sources[0x29]	2945	1		T5	2		T31	4		T27	5
valid_sources[0x2a]	2739	1		T31	1		T27	2		T29	12
valid_sources[0x2b]	2745	1		T9	2		T31	16		T23	1
valid_sources[0x2c]	2494	1		T8	1		T9	2		T31	2
valid_sources[0x2d]	2627	1		T5	2		T31	2		T29	12
valid_sources[0x2e]	2505	1		T31	5		T27	3		T29	15
valid_sources[0x2f]	3979	1		T5	2		T12	1		T31	6
valid_sources[0x30]	2683	1		T5	1		T9	2		T31	2
valid_sources[0x31]	2944	1		T9	1		T31	3		T27	1
valid_sources[0x32]	2521	1		T5	2		T31	5		T27	2
valid_sources[0x33]	2959	1		T5	1		T8	1		T31	2
valid_sources[0x34]	2852	1		T5	1		T14	1		T31	7
valid_sources[0x35]	2701	1		T8	1		T14	1		T12	1
valid_sources[0x36]	2614	1		T31	8		T27	3		T29	8
valid_sources[0x37]	2659	1		T5	1		T14	1		T9	1
valid_sources[0x38]	2635	1		T9	1		T31	9		T27	5
valid_sources[0x39]	2526	1		T5	1		T11	4		T15	5
valid_sources[0x3a]	2625	1		T5	4		T14	1		T9	2
valid_sources[0x3b]	2476	1		T8	1		T31	4		T27	2
valid_sources[0x3c]	2766	1		T5	1		T31	10		T27	8
valid_sources[0x3d]	2563	1		T14	1		T31	3		T27	5
valid_sources[0x3e]	2675	1		T31	1		T27	3		T29	11
valid_sources[0x3f]	3021	1		T12	2		T31	6		T29	5
valid_sources[0x40]	2832	1		T9	1		T27	4		T75	12
valid_sources[0x41]	2596	1		T5	1		T12	2		T9	1
valid_sources[0x42]	2669	1		T27	4		T29	15		T28	3
valid_sources[0x43]	2651	1		T14	1		T31	1		T27	3
valid_sources[0x44]	2776	1		T5	5		T31	1		T27	1
valid_sources[0x45]	2903	1		T31	1		T27	6		T29	15
valid_sources[0x46]	2736	1		T8	1		T14	1		T15	1
valid_sources[0x47]	3030	1		T5	1		T15	3		T66	1
valid_sources[0x48]	2683	1		T31	3		T27	2		T29	12
valid_sources[0x49]	2888	1		T5	1		T31	3		T27	5
valid_sources[0x4a]	2783	1		T9	1		T66	3		T31	2
valid_sources[0x4b]	2432	1		T5	1		T31	8		T27	2
valid_sources[0x4c]	2650	1		T5	2		T31	8		T27	4
valid_sources[0x4d]	2506	1		T5	1		T14	2		T12	1
valid_sources[0x4e]	2733	1		T27	4		T75	3		T29	12
valid_sources[0x4f]	2644	1		T5	2		T8	1		T27	2
valid_sources[0x50]	3298	1		T31	6		T27	6		T29	24
valid_sources[0x51]	2699	1		T27	1		T29	11		T30	35
valid_sources[0x52]	2576	1		T5	1		T27	4		T29	7
valid_sources[0x53]	2820	1		T5	1		T9	2		T31	1
valid_sources[0x54]	2705	1		T9	1		T31	7		T27	5
valid_sources[0x55]	2857	1		T31	3		T27	5		T29	2
valid_sources[0x56]	2775	1		T27	5		T75	8		T29	12
valid_sources[0x57]	2627	1		T5	1		T11	6		T14	3
valid_sources[0x58]	2867	1		T15	11		T66	10		T31	5
valid_sources[0x59]	2708	1		T9	2		T31	2		T27	3
valid_sources[0x5a]	2607	1		T5	1		T8	1		T9	2
valid_sources[0x5b]	2521	1		T14	1		T9	2		T31	6
valid_sources[0x5c]	5005	1		T5	2		T14	2		T31	7
valid_sources[0x5d]	2606	1		T14	1		T31	5		T29	25
valid_sources[0x5e]	4113	1		T8	1		T31	1		T27	7
valid_sources[0x5f]	2788	1		T31	6		T27	2		T29	10
valid_sources[0x60]	2795	1		T5	2		T31	10		T27	3
valid_sources[0x61]	2938	1		T8	1		T31	9		T27	4
valid_sources[0x62]	2530	1		T5	1		T14	3		T31	11
valid_sources[0x63]	3279	1		T9	1		T31	9		T27	4
valid_sources[0x64]	2712	1		T5	1		T14	1		T15	4
valid_sources[0x65]	2481	1		T31	3		T27	1		T29	11
valid_sources[0x66]	2425	1		T27	8		T29	10		T28	2
valid_sources[0x67]	2966	1		T31	13		T27	1		T29	9
valid_sources[0x68]	2628	1		T66	4		T27	1		T29	11
valid_sources[0x69]	2602	1		T5	2		T15	14		T9	1
valid_sources[0x6a]	2992	1		T31	5		T27	1		T29	15
valid_sources[0x6b]	2902	1		T66	1		T29	15		T28	3
valid_sources[0x6c]	3028	1		T14	1		T31	2		T27	4
valid_sources[0x6d]	2753	1		T31	1		T27	1		T29	17
valid_sources[0x6e]	2486	1		T14	3		T27	2		T29	4
valid_sources[0x6f]	2853	1		T11	1		T14	1		T12	2
valid_sources[0x70]	2923	1		T9	1		T31	12		T27	2
valid_sources[0x71]	2749	1		T8	1		T31	6		T27	2
valid_sources[0x72]	2873	1		T31	21		T27	2		T29	14
valid_sources[0x73]	2739	1		T31	5		T27	4		T29	20
valid_sources[0x74]	2664	1		T31	3		T27	6		T29	9
valid_sources[0x75]	3244	1		T12	1		T31	1		T27	2
valid_sources[0x76]	3357	1		T5	1		T11	2		T9	2
valid_sources[0x77]	3069	1		T5	1		T14	3		T31	4
valid_sources[0x78]	2756	1		T12	1		T31	6		T27	5
valid_sources[0x79]	2820	1		T5	1		T31	5		T27	4
valid_sources[0x7a]	2541	1		T15	4		T9	1		T27	2
valid_sources[0x7b]	3358	1		T8	2		T23	1		T27	5
valid_sources[0x7c]	2824	1		T5	1		T12	2		T31	8
valid_sources[0x7d]	2744	1		T12	1		T9	1		T31	3
valid_sources[0x7e]	2538	1		T9	1		T31	5		T27	7
valid_sources[0x7f]	2694	1		T9	1		T31	6		T29	15
valid_sources[0x80]	3234	1		T31	1		T27	3		T29	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

276037

1

T5

3

T6

8

T7

6

values[0x0]

all_enables

biggest_size

127281

1

T5

24

T6

16

T8

8

values[0x1]

all_enables

biggest_size

126059

1

T5

12

T6

13

T8

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4608	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18974	1		T1	2		T3	3		T4	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9348	1		T31	6		T23	12		T27	7
values[0x0]	6991	1		T1	5		T2	2		T3	2
values[0x1]	7243	1		T1	4		T2	3		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3585	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19997	1		T1	2		T3	3		T4	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	85	1		T24	21		T67	1		T69	7
valid_sources[0x01]	65	1		T44	1		T24	7		T25	1
valid_sources[0x02]	50	1		T117	1		T24	3		T25	2
valid_sources[0x03]	84	1		T4	1		T24	10		T25	3
valid_sources[0x04]	118	1		T28	5		T24	31		T25	1
valid_sources[0x05]	104	1		T2	3		T50	19		T24	11
valid_sources[0x06]	75	1		T1	2		T28	15		T30	1
valid_sources[0x07]	64	1		T24	13		T25	4		T67	1
valid_sources[0x08]	105	1		T24	13		T25	5		T67	2
valid_sources[0x09]	59	1		T31	2		T24	7		T25	1
valid_sources[0x0a]	128	1		T118	18		T117	1		T31	3
valid_sources[0x0b]	108	1		T119	1		T24	6		T25	2
valid_sources[0x0c]	96	1		T24	17		T25	1		T68	16
valid_sources[0x0d]	82	1		T24	16		T67	2		T69	1
valid_sources[0x0e]	233	1		T24	5		T67	1		T69	7
valid_sources[0x0f]	54	1		T120	1		T24	10		T69	4
valid_sources[0x10]	68	1		T121	1		T24	8		T25	2
valid_sources[0x11]	51	1		T122	1		T123	3		T30	1
valid_sources[0x12]	174	1		T44	1		T24	2		T68	22
valid_sources[0x13]	78	1		T24	1		T71	6		T74	1
valid_sources[0x14]	95	1		T19	1		T24	19		T69	1
valid_sources[0x15]	439	1		T27	10		T24	2		T25	3
valid_sources[0x16]	211	1		T124	5		T125	1		T24	9
valid_sources[0x17]	77	1		T24	14		T25	1		T67	1
valid_sources[0x18]	62	1		T121	1		T24	4		T25	2
valid_sources[0x19]	58	1		T122	1		T75	2		T24	3
valid_sources[0x1a]	79	1		T117	1		T31	1		T24	4
valid_sources[0x1b]	826	1		T46	2		T122	1		T30	1
valid_sources[0x1c]	78	1		T126	1		T127	1		T23	3
valid_sources[0x1d]	176	1		T23	1		T28	1		T24	11
valid_sources[0x1e]	57	1		T24	14		T73	1		T74	4
valid_sources[0x1f]	103	1		T128	1		T31	1		T30	2
valid_sources[0x20]	68	1		T23	2		T30	1		T24	2
valid_sources[0x21]	66	1		T47	3		T23	2		T24	2
valid_sources[0x22]	111	1		T129	1		T28	1		T24	11
valid_sources[0x23]	52	1		T30	2		T69	1		T73	1
valid_sources[0x24]	79	1		T3	1		T30	1		T24	27
valid_sources[0x25]	88	1		T3	1		T130	6		T117	1
valid_sources[0x26]	93	1		T122	1		T128	1		T25	1
valid_sources[0x27]	163	1		T122	1		T30	1		T24	17
valid_sources[0x28]	64	1		T27	1		T24	2		T68	1
valid_sources[0x29]	72	1		T117	1		T24	9		T69	6
valid_sources[0x2a]	160	1		T29	2		T28	1		T24	7
valid_sources[0x2b]	56	1		T24	7		T67	4		T68	6
valid_sources[0x2c]	73	1		T24	10		T69	1		T73	2
valid_sources[0x2d]	72	1		T128	1		T23	1		T24	12
valid_sources[0x2e]	179	1		T128	1		T28	1		T24	20
valid_sources[0x2f]	83	1		T24	4		T25	1		T67	2
valid_sources[0x30]	46	1		T44	2		T24	4		T25	1
valid_sources[0x31]	92	1		T46	2		T122	1		T30	1
valid_sources[0x32]	61	1		T24	3		T25	2		T69	7
valid_sources[0x33]	96	1		T52	1		T23	1		T24	3
valid_sources[0x34]	57	1		T23	2		T24	13		T25	1
valid_sources[0x35]	86	1		T47	1		T24	1		T73	1
valid_sources[0x36]	156	1		T131	14		T29	1		T24	21
valid_sources[0x37]	66	1		T75	2		T24	1		T25	1
valid_sources[0x38]	49	1		T24	1		T67	2		T69	3
valid_sources[0x39]	53	1		T44	2		T23	1		T25	3
valid_sources[0x3a]	90	1		T24	8		T25	1		T68	5
valid_sources[0x3b]	78	1		T24	23		T69	4		T74	2
valid_sources[0x3c]	63	1		T24	14		T25	1		T74	2
valid_sources[0x3d]	58	1		T42	3		T24	9		T25	1
valid_sources[0x3e]	93	1		T44	1		T23	1		T24	9
valid_sources[0x3f]	69	1		T30	1		T24	7		T69	1
valid_sources[0x40]	77	1		T23	1		T24	4		T67	1
valid_sources[0x41]	51	1		T24	7		T102	1		T96	1
valid_sources[0x42]	49	1		T127	2		T24	3		T25	1
valid_sources[0x43]	57	1		T24	12		T69	4		T74	1
valid_sources[0x44]	164	1		T24	5		T25	2		T68	3
valid_sources[0x45]	48	1		T125	1		T24	10		T25	1
valid_sources[0x46]	63	1		T4	1		T24	25		T25	1
valid_sources[0x47]	90	1		T28	1		T24	6		T67	1
valid_sources[0x48]	81	1		T132	1		T25	1		T67	2
valid_sources[0x49]	65	1		T25	1		T68	8		T73	1
valid_sources[0x4a]	70	1		T24	7		T25	2		T67	1
valid_sources[0x4b]	55	1		T23	2		T30	1		T24	4
valid_sources[0x4c]	82	1		T108	2		T23	1		T24	14
valid_sources[0x4d]	72	1		T24	13		T68	2		T73	1
valid_sources[0x4e]	81	1		T28	2		T24	10		T25	1
valid_sources[0x4f]	77	1		T47	1		T24	1		T68	4
valid_sources[0x50]	67	1		T128	1		T23	1		T24	19
valid_sources[0x51]	134	1		T128	1		T23	1		T30	1
valid_sources[0x52]	67	1		T3	1		T24	4		T69	1
valid_sources[0x53]	93	1		T24	3		T25	2		T68	2
valid_sources[0x54]	96	1		T45	11		T23	1		T24	17
valid_sources[0x55]	141	1		T24	11		T68	1		T69	2
valid_sources[0x56]	109	1		T24	13		T25	1		T67	2
valid_sources[0x57]	107	1		T24	7		T25	1		T68	5
valid_sources[0x58]	96	1		T133	1		T23	3		T29	4
valid_sources[0x59]	101	1		T134	3		T24	39		T25	2
valid_sources[0x5a]	67	1		T128	1		T30	1		T24	4
valid_sources[0x5b]	75	1		T23	2		T24	4		T69	11
valid_sources[0x5c]	139	1		T44	1		T135	10		T30	1
valid_sources[0x5d]	58	1		T126	1		T31	1		T23	1
valid_sources[0x5e]	66	1		T51	1		T46	1		T122	1
valid_sources[0x5f]	61	1		T128	1		T23	1		T24	7
valid_sources[0x60]	53	1		T4	1		T117	1		T24	5
valid_sources[0x61]	54	1		T74	3		T102	1		T136	5
valid_sources[0x62]	75	1		T47	1		T30	1		T24	10
valid_sources[0x63]	40	1		T30	2		T24	4		T73	4
valid_sources[0x64]	68	1		T137	6		T23	1		T24	10
valid_sources[0x65]	68	1		T30	1		T24	4		T25	3
valid_sources[0x66]	76	1		T3	1		T124	2		T24	20
valid_sources[0x67]	76	1		T24	10		T25	3		T68	1
valid_sources[0x68]	69	1		T23	1		T30	1		T24	7
valid_sources[0x69]	126	1		T3	1		T30	1		T24	4
valid_sources[0x6a]	77	1		T138	4		T30	4		T24	9
valid_sources[0x6b]	58	1		T126	1		T30	1		T24	7
valid_sources[0x6c]	87	1		T24	9		T69	2		T73	3
valid_sources[0x6d]	50	1		T24	6		T67	1		T69	4
valid_sources[0x6e]	83	1		T129	3		T24	3		T25	1
valid_sources[0x6f]	76	1		T32	6		T30	1		T24	17
valid_sources[0x70]	81	1		T44	2		T30	1		T24	5
valid_sources[0x71]	81	1		T30	2		T24	17		T25	1
valid_sources[0x72]	90	1		T139	1		T30	1		T24	8
valid_sources[0x73]	71	1		T1	3		T30	1		T24	10
valid_sources[0x74]	184	1		T140	2		T117	1		T24	15
valid_sources[0x75]	108	1		T24	12		T69	4		T74	1
valid_sources[0x76]	44	1		T28	6		T24	4		T69	1
valid_sources[0x77]	80	1		T108	1		T24	14		T67	2
valid_sources[0x78]	301	1		T120	1		T119	1		T24	3
valid_sources[0x79]	53	1		T138	4		T24	1		T69	1
valid_sources[0x7a]	97	1		T140	2		T141	4		T24	22
valid_sources[0x7b]	142	1		T24	16		T67	4		T77	2
valid_sources[0x7c]	85	1		T19	1		T53	1		T46	1
valid_sources[0x7d]	85	1		T23	1		T29	1		T28	1
valid_sources[0x7e]	75	1		T24	7		T25	2		T67	1
valid_sources[0x7f]	90	1		T44	1		T127	1		T24	4
valid_sources[0x80]	130	1		T24	4		T67	2		T68	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6517

1

T31

4

T23

12

T27

4

values[0x0]

all_enables

biggest_size

6328

1

T1

1

T3

1

T4

2

values[0x1]

all_enables

biggest_size

6129

1

T1

1

T3

2

T18

2